Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1997-08-14
2001-11-27
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S041000, C326S047000
Reexamination Certificate
active
06323678
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an integrated circuit device having programmable junctions, and more particularly to a structure of and a method of designing programmable junctions of a field programmable gate array (FPGA) or a multimicroprocessor system.
FPGAs comprise a matrix of logic cells capable of performing various logic operations and a plurality of intercell signal lines disposed between the logic cells. The intercell signal lines are connectable to input/output terminals of the logic cells to connect the logic cells in an optional combination for thereby achieving a desired logic circuit. Therefore, junctions between the intercell signal lines and the input/output terminals of the logic cells have a programmable structure, i.e., comprise a set or cluster of program switches.
One simple approach to connecting the logic cells with greater flexibility is to provide as many program switches as possible. Consequently, conventional FPGAs have program switches so positioned at the junctions as to be able to connect all commutable input terminals of the logic cells freely to intercell signal lines. Alternatively, those program switches are positioned to substantially perform such a function.
An FPGA chip has an area of a matrix of logic cells, an area of intercell buses comprising a plurality of intercell signal lines, junctions comprising a plurality of program switches, and a switch block connecting horizontal and vertical intercell signal lines. The density of an FPGA logic circuit is substantially inversely proportional to the total number of program switches at the junctions and the area of each of the program switches for the reason that most of the area of the FPGA chip is occupied by the junctions having the program switches.
In order to increase the number of logic gates that can be realized per unit area so as to increase an area efficiency, it is necessary to reduce the total number of program switches thereby to reduce the area of the junctions.
However, since the program switches of the conventional FPGAs are so positioned as to be able to connect all the commutable input terminals of the logic cells freely to the intercell signal lines, the area efficiency of the resultant logic circuit tends to be low. This problem holds true for the junctions of a multimicroprocessor system in which microprocessors are connectable in an optional combination.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an integrated circuit device which has programmable junctions with program switches optimized in number and placement for increasing an area efficiency without lowering a connection efficiency.
Another object of the present invention is to provide an integrated circuit device which has programmable junctions with program switches optimized in number and placement for increasing an area efficiency without lowering a connection efficiency and also for increasing a circuit speed.
Still another object of the present invention is to provide a method of designing an integrated circuit device which has junctions with a process of arranging program switches at the junctions for increasing an area efficiency without lowering a connection efficiency.
According to the present invention, there is provided an integrated circuit device comprising a plurality of first signal lines, n second signal lines intersecting with the first signal lines, and a junction having programmable switches positioned at intersections between the first signal lines and the second signal lines, the switches being placed at positions for connecting n of the first signal lines to at least one combination of the n second signal lines and for connecting optional m (m<n) of the first signal lines simultaneously to any of the second signal lines.
According to the present invention, there is also provided a field gate array comprising a matrix of logic cells each having n input terminals, a plurality of intercell buses disposed between the logic cells and each having a plurality of intercell signal lines, and junctions disposed around the logic cells and each including the intercell signal lines, n input terminal lines intersecting with the intercell signal lines and connected to the input terminals, and programmable switches disposed at intersections between the intercell signal lines and the input terminal lines, the switches being placed at positions for connecting n of the first signal lines to at least one combination of the n input terminal lines and for connecting optional m (m<n) of the intercell signal lines simultaneously to any of the input terminal lines.
With the above arrangement, the junction comprises a minimum number of switches and hence has as small an area as possible.
Maximum and minimum numbers of the switches connected to the intercell signal lines differ from each other by at most 1. Alternatively, maximum and minimum numbers of the switches connected to the input terminal lines differ from each other by at most 1. Loads on the switches connected to the intercell signal lines or the input terminal lines are thus uniformized for thereby increasing the operating speed of the field programmable gate array.
According to the present invention, there is further provided a method of designing an integrated circuit device having a plurality of first signal lines, n second signal lines intersecting with the first signal lines, and a junction having programmable switches positioned at intersections between the first signal lines and the second signal lines, the comprising the steps of placing the switches in a first region of the junction at intersections between n of the first signal lines and the n second signal lines, such that the number of switches connected to each of the first signal lines is 1 and the number of switches connected to each of the second signal lines is 1, placing m (m<n) of the switches on the first signal lines in a second region of the junction outside of the first region, moving switches placed on the first signal lines along the first signal lines for uniformizing the numbers of switches connected to the second signal lines in the second region, and moving switches placed on the second signal lines in the second region along the second signal lines for uniformizing the numbers of switches connected to the first signal lines in the second region and the first region.
According to the present invention, there is also provided a method of designing a field programmable gate array, having a matrix of logic cells each having n input terminals, a plurality of intercell buses disposed between the logic cells and each having a plurality of intercell signal lines, and junctions disposed around the logic cells and each including the intercell signal lines, n input terminal lines intersecting with the intercell signal lines and connected to the input terminals, and programmable switches disposed at intersections between the intercell signal lines and the input terminal lines, the method comprising the steps of placing the switches in a first region of the junction at intersections between n of the intercell signal lines and the n input terminal lines, such that the number of switches connected to each of the intercell signal lines is 1 and the number of switches connected to each of the input terminal lines is 1, placing m (m<n) of the switches on the intercell signal lines in a second region of the junction outside of the first region, moving switches placed on the intercell signal lines along the intercell signal lines for uniformizing the numbers of switches connected to the input terminal lines in the second region, and moving switches placed on the input terminal lines in the second region along the input terminal lines for uniformizing the numbers of switches connected to the intercell signal lines in the second region and the first region.
According to the above methods, it is possible to place a minimum number of switches at optimum positions.
The principles of the present invention are applicable t
Armstrong, Westerman, Hattori, McLeland & Naughton, LLP.
Fujitsu Limited
Paik Steven S.
Tokar Michael
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