Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond
Reexamination Certificate
2000-02-23
2002-04-02
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Solder wettable contact, lead, or bond
C257S693000, C257S678000, C257S738000, C257S737000
Reexamination Certificate
active
06365976
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of semiconductor devices and processes and more specifically to molded low-cost ball grid array and chip scale packages and method of fabricating depressions for receiving solder balls.
DESCRIPTION OF THE RELATED ART
The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's “law”), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
While plastic ball grid array (BGA) and chip-scale packages (CSP) became very popular in the last few years, they have been limited to fully participate in the trends for Moore's law due to a number of shortcomings. It turned out to be difficult to reduce the cost of BGAs and CSPs due to high content of plastic materials and the fixed number of fabrication process steps. The reliability of plastic BGAs and CSPs suffers from sensitivity to thermo-mechanical stress and moisture absorption. It is difficult to adjust the package designs to custom requirements; consequently, the package designs are not flexible enough to fit the general application trends towards smaller package outlines and thinner profiles.
Known technology focuses the attention for developing BGA and CSP package designs and processes on devices with high lead counts (or solder ball numbers) and neglects the specific needs of BGAs and CSPs for smaller lead (or solder ball) numbers. Thus, opportunities in the huge application market requiring specifically low solder ball numbers go unattended.
In the present state of the art, plastic packages with small pin count use stamped or etched leadframes; these leadframes represent the dominant materials cost in these packages. Plastic BGAs and CSPs, use patterned polyimide films are as substrates for mounting the semiconductor chips; these films represent the dominant materials cost in these packages. In addition, the techniques used in present technology for attaching solder balls (or bumps) to the packages is unsatisfactory because of problems related to ball adhesion, missing balls, or ball duplication. The fabrication processes employed and the inspections required are hindering cost reductions.
SUMMARY OF THE INVENTION
According to the present invention for integrated circuit (IC) devices, the molding process for encapsulating the device is used to form depressions of suitable size and shape to receive solder balls, while these depressions are structured such that they have an electrically conductive and solderable surface which is electrically connected to the input/output terminals of the IC chip.
The present invention is related to high density ICs, especially those having low or modest numbers of inputs/outputs or bonding pads, further to devices using an electrically conductive or metallic substrate, to which they are usually connected by wire bonding, and also to devices requiring small package outlines and low profiles. These ICs can be found in many semiconductor device families such as processors, digital and analog devices, mixed signal and standard linear and logic products, telephone, RF and telecommunications devices, intelligent power devices, and both large and small area chip categories. The invention helps to insure built-in quality and reliability in applications such as cellular communications, pagers, hard disk drives, laptop computers, and medical instrumentation.
The invention provides some material modifications and several simplifications of basic process steps commonly practiced in semiconductor assembly and packaging technology so that significant manufacturing cost reductions are achieved. The chips are mounted on substrates provided as thin foils in the thickness range of about 10 to 75 &mgr;m. In this thickness range, the foils respond to the pressure during conventional transfer molding processes, move against the steel walls of the mold cavity and align smoothly to the surface contours of the walls. Dimples reaching into the molded material, yet covered with a solderable surface, can thus be created; they serve as depressions holding the solder “balls” reliably and can be used to best advantage in solder attachments. The amount of deformation, or “inside curvature”, to which certain foil materials can stretch in order to move from their original flat configuration to a curved configuration, has been determined by this invention. Ball-receiving depressions can be created between about 150 and 230 &mgr;m deep using an annealed copper foil of about 30 to 40 &mgr;m thickness.
It is an aspect of the present invention to be applicable to a variety of different ball grid array and chip-scale packages, especially those with a “ball” count of about 4 to 80. The most frequently used range is between about 8 and 48 “balls”.
Another aspect of the present is to simplify the positioning of pre-fabricated solder balls on the device package by creating ball-receiving depressions in the flat package contour during the package molding process.
Another aspect of the present invention is to strengthen the solder ball attachment to the package by enlarging the attachment area.
Another aspect of the present invention is to enhance the package reliability by improving the adhesion between the molding compound and the metal foil used for electrical contacts to the outside world.
Another aspect of the present invention is to introduce manufacturing steps which contribute to the trends towards packages with lower overall profiles and smaller outlines, thus contributing to device space conservation.
Another aspect of the present invention is to improve product quality by process simplification, and to enhance reliability assurance by controlling thermomechanical stress, minimizing moisture absorption, and general in-process control at no extra cost.
Another aspect of the present invention is to introduce assembly concepts for thin profile packages which are flexible so that they can be applied to many families of semiconductor products, and are general so that they can be applied to several future generations of products.
These aspects have been achieved by the teachings of the invention concerning methods suitable for mass production. Various modifications have been successfully employed to satisfy different selections of product geometries and materials.
In one embodiment of the present invention, the size of the ball-receiving depression and thus the stretch of the foil material necessary to achieve this depression is used to produce devices of certain low profiles.
In another embodiment of the invention, the number of depressions and the arrangement in rows of solder ball receptors is used to produce devices of certain small ball grid array and chip-scale package outlines.
In another embodiment of the invention, the shape of the depressions has been modified from semi-spherical to truncated pyramid. This modification not only enhances solder ball attachment and molding compound adhesion to the metal foil, but also lowers the cost of manufacturing the bottom half of the mold by simplifying the work and the tools needed for preparing the surface contours of the steel.
In another embodiment of the invention, a simple mechanical grinding technique is employed to achieve electrical separation of the pac
Carter, Jr. Buford H.
Davis Dennis D.
Johnson Richard E.
Kee David R.
Clark Jhihan B
Honeycutt Gary C.
Navarro Arthur I.
Telecky Fred
Texas Instruments Incorporated
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