Integrated circuit device isolation methods using high...

Details Integrated circuit device isolation methods using high... Integrated circuit device isolation methods using high...

2000-05-12

2003-03-25

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S700000, C438S702000

Reexamination Certificate

active

06537914

ABSTRACT:

RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 99-16974, filed May 12, 1999, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to isolation methods for integrated circuit devices and, more particularly, to trench isolation methods for integrated circuit devices.
BACKGROUND OF THE INVENTION
As integrated circuit devices become more highly integrated and include finer geometries, it may become increasingly important to reduce the size of isolation regions that are used to isolate active devices, such as transistors, from one another. The initial formation of isolation regions may determine the size of an active region and the process margins for subsequent processing. Accordingly, reduction of the size of the isolation regions may be desirable.
LOCal Oxidation of Silicon (LOCOS) may be used for fabricating isolation regions in integrated circuits. The LOCOS process is generally relatively simple. In highly integrated devices, however, such as 256 MBB DRAM devices, as the width of the isolation region is reduced, a punchthrough may be caused by “bird's beak” during oxidation. This may reduce the thickness of a field oxide film and may reduce the size of the active regions.
An isolation method may also use a trench, rather than forming a field oxide layer by thermal oxidation. In trench isolation methods, a trench is formed on the integrated circuit device and is filled with an insulating material, such as an oxide layer, to form an isolation region that can be smaller than that formed by the LOCOS method. Moreover, problems associated with the LOCOS method and problems associated with thermal oxidation may be controlled.
FIG. 1
illustrates fabrication steps for a conventional shallow trench isolation (STI) method. As shown in
FIG. 1
, a pad oxide layer is formed on an integrated circuit substrate, such as a semiconductor substrate, at block
10
. A silicon nitride layer is then formed on the pad oxide layer at block
12
. A photoresist layer is formed on the silicon nitride layer at block
14
. The photoresist layer is patterned by conventional methods to form a photoresist mask pattern. At block
16
, the silicon nitride layer is patterned using the patterned photoresist as a mask. The photoresist is then removed at block
18
. The silicon nitride layer is then used to form a trench at block
20
. An insulation layer is formed in the trench and on the substrate to bury the trench at block
22
. Chemical-mechanical polishing (CMP) is then used to planarize the trench at block
24
. The silicon nitride layer is then removed at block
26
. The details of conventional trench isolation are generally known to those having skill in the art and need not be described further herein.
The STI method described in the foregoing may avoid thermal oxidation problems associated with the LOCOS method because the isolation layer is not formed by a local oxidation step. Nevertheless, the conventional STI method may be relatively complicated, which may result in higher manufacturing costs than may be incurred with the LOCOS method. In addition, the conventional STI method may result in thick silicon nitride layers formed on both sides of the trench, which may increase the aspect ratio of the trench. An increase in the aspect ratio of the trench due to thick silicon nitride layers may cause poor step coverage of a chemical vapor deposition (CVD) oxide layer, which may generate voids in the trench. Consequently, there exists a need for improved trench isolation methods.
SUMMARY OF THE INVENTION
The present invention may simplify trench isolation methods for integrated circuits and may also provide improved performance of integrated circuits by reducing irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. According to embodiments of the present invention, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO
2
group abrasive to form an isolation layer in the trench. Advantageously, the CMP selectivity ratio of a slurry that includes a CeO
2
group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.
According to other embodiments of the present invention, a photoresist mask pattern may be formed on the substrate surface prior to the formation of a trench therein. This photoresist mask pattern may then be removed from the substrate surface after the trench is formed and prior to the formation of the insulation layer on the substrate surface and in the trench.
According to still other embodiments of the present invention, the CMP slurry may further include an anionic surfactant, such as polyvinylsulphonate (PVS), and the pH of the slurry may be maintained at approximately 7. This may allow the zeta potential of the substrate surface to be a positive value while the zeta potential of the insulation layer is a negative value. The anionic surfactant may then adhere to the substrate surface thereby suppressing reaction of the CeO
2
group abrasive therewith. Preferably, the slurry has a CMP selectivity ratio of at least 1:10 between the substrate surface and the insulation layer, respectively.
According to still other embodiments of the present invention, a thermal oxide layer may be formed on the substrate surface and in the trench after the trench is formed and prior to the formation of the insulation layer on the substrate surface and in the trench. In addition, thermal treatment may be performed on the insulation layer after it is formed on the substrate surface and in the trench.
According to still other embodiments of the present invention, after chemical-mechanical polishing, a step may be formed between the isolation layer and the substrate surface to form an alignment key for subsequent processing. The step may be formed by etching the substrate surface to recess the substrate surface relative to the isolation layer.
According to still other embodiments of the present invention, after chemical-mechanical polishing, an oxide layer may be formed on the isolation layer and ions may be implanted through the oxide layer. The ions may be used to form wells and channel stops and to control the threshold voltage of devices that are subsequently formed.
In alternative embodiments of the present invention, a substrate surface is etched to form a trench and a nitride liner is formed on the substrate surface and in the trench. An insulation layer is then formed on the nitride liner such that the trench is filled. The insulation layer is then chemical-mechanical polished to form an isolation layer in the trench.
According to other embodiments of the present invention, a nitride layer may be formed directly on the substrate surface prior to the formation of a trench therein. The nitride layer may comprise silicon oxynitride (SiON) and, along with the nitride liner, may be used as a CMP stop to improve the uniformity of the thickness of the isolation layer.
According to still other embodiments of the present invention, a photoresist mask pattern may be formed on the substrate surface prior to the formation of the trench therein. This photoresist mask pattern may then be removed from the substrate surface after the trench is formed and prior to the formation of the nitride liner on the substrate surface and in the trench.
According to still other embodiments of the present invention, the chemical-mechanical polishing may be performed using a slurry that comprises a CeO
2
group abrasive and an anionic surfactant. The CMP slurry may further include an anionic surfactant and the pH of the slurry may be maintained at approximately 7 to facilitate polishing

Affiliated with

Also associated with

Rating

Integrated circuit device isolation methods using high... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit device isolation methods using high..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit device isolation methods using high... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3069263