Integrated circuit device interconnection techniques

Details Integrated circuit device interconnection techniques Integrated circuit device interconnection techniques

1998-09-16

2001-01-16

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C257S758000

Reexamination Certificate

active

06174803

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to interconnection and routing techniques for integrated circuit components, and more particularly, but not exclusively relates to a multilevel architecture having greater layout flexibility that facilitates higher routing and interconnection density.
The need for faster and more complex electronic components fuels a desire to decrease the size of integrated circuit components. Correspondingly, it is often desirable to reduce the size of electrical interconnects for these components while maintaining high reliability and low electrical resistance. Highly conductive materials, such as metals, are often necessary for forming integrated circuit interconnects. One approach is to form a stack of interconnected layers that each include a pattern of elongate metal traces or via plugs insulated from one another by a dielectric. Usually, vertical via plugs in one layer are used to provide electrical connection between adjacent layers. Photolithographic patterning and associated etching processes typically provide the desired pattern for each layer. Unfortunately, the current desire to shrink the critical dimensions of active integrated circuit transistors deep into the submicron range (e.g. less than about 0.25 microns) limits the ability to correspondingly reduce metal conductor size through direct metal etching. As a result, new approaches have been sought to provide for the corresponding increased density of integrated circuit device interconnections.
FIG. 1
illustrates further limitations of existing approaches. Integrated circuit
50
of
FIG. 1
includes substrate
52
with component connection sites
56
a,
56
b
therealong. Oxide layer
60
covers substrate
52
and defines via holes for metal via plugs
62
a,
62
b
to electrically contact sites
56
a,
56
b,
respectively. Layer
64
is formed on top of layer
60
to provide a pattern of metal traces
66
insulated from each other by a dielectric—typically a silica (silicon dioxide) based material. Two of traces
66
are shown in electrical contact with plugs
62
a,
62
b
to provide selected electrical contact with sites
56
a,
56
b,
respectively.
Layer
70
is formed on layer
64
and includes a pattern of metallic via plugs
72
insulated from each other by a dielectric—also usually a silica-based material. Layer
74
is formed on layer
70
and includes a pattern of metal traces
76
insulated from each other in a similar manner to layer
64
. Plugs
72
of layer
70
interconnect selected traces
66
and
76
of layers
64
and
74
, respectively, to provide a predetermined wiring pattern for circuit
50
. It should be noted that traces
66
include a crossunder connection specifically designated by reference numeral
66
a
to provide electrical coupling between two traces
76
of layer
74
that are separated by another trace specifically designated by reference numeral
76
b.
Similarly, traces
76
include a crossover connection designated by reference numeral
76
a
to provide electrical coupling between two traces
66
of layer
64
. Notably, crossover
76
a
is routed around the trace specifically designated by reference numeral
66
b
by elevation to the next metallization level of layer
74
. The crossover and crossunder connections have a longitudinal orientation that is generally perpendicular to the longitudinal orientation of other traces contained in the same layer. This orientation tends to limit the number of traces that may be included in a given layer.
A similar limitation to the “packing density” of integrated circuit interconnects arises from the occupation of layer “real estate” by dedicated, long-distance power supply bus traces in the same layer as long-distance signal carrying traces. Typically, power supply traces are about 10 to 50 times wider than other types of signal routings. Also, the more costly dielectric materials often utilized to preserve the integrity of long-distance, time-varying signal conductors are usually not needed for power supply conductors. Traces designated by reference numerals
66
b,
76
b
in layers
64
,
74
, are representative of power supply bus connections of existing integrated circuit arrangements.
Thus, a need remains for techniques to further increase the density of integrated circuit component interconnects. The present invention satisfies this need, generally improves integrated circuit layout flexibility, and provides other significant benefits and advantages.
SUMMARY OF THE INVENTION
The present invention relates to techniques for interconnecting integrated circuit components. Various aspects of the invention are novel, nonobvious, and provide various advantages. While the actual nature of the invention covered herein can only be determined with reference to the claims appended hereto, certain forms that are characteristic of the preferred embodiments disclosed herein are described briefly as follows.
One form of the present invention includes a multilevel interconnection technique having crossover, crossunder, or local interconnects in a different connection layer than routing interconnects. These different connection layers are preferably separated by an insulative hard mask that functions as an etch stop layer relative to a dielectric included in the connection layers. As used herein, a “routing interconnect” refers to an electrical connection that traverses several integrated circuit components; and a “local interconnect” refers to an electrical connection of two or more routing interconnects, two or more connection regions of the same integrated circuit component, or two or more connection regions of adjacent integrated circuit components. As a result, routing interconnects typically provide longer range, lower resistance electrical coupling of components that are remotely located from each other. It is also preferred that the connection layer dielectric be comprised of a silica-based material and that the insulative hard mask be comprised of a silicon nitride or silicon oxynitride based material.
Another form includes an integrated circuit device with a number of electronic components along a semiconductor substrate and a first connection layer comprised of a first dielectric and a first number of conductors in selective electrical contact with the components. A first insulative layer is positioned on the first connection layer with a first pattern of openings therethrough. Also included is a second connection layer comprised of a second dielectric and a second number of conductors, a second insulative layer on the second connection layer with a second pattern of openings therethrough, and a third connection layer on the second insulative layer. The third connection layer is comprised of a third dielectric and a third number of conductors. The third dielectric is etch selective to the second insulative layer. The second and third conductors are in contact with the second insulative layer and at least one of the second conductors crosses at least one of the third conductors, being electrically isolated therefrom by the second insulative layer. The second conductors may be utilized to form a number of overpass or crossover connections between the first conductors and a number of underpass or crossunder connections between the third conductors. Further, the second conductors may include one or more power bus distribution conductors to free the first and third layers from providing the significant amount of space usually needed to accommodate power supply conductors. As a result, the first and third layers may have a comensurately higher routing interconnect density.
A further form includes provision for compatibility with Damascene integrated circuit architecture. This form includes providing an integrated circuit device with a number of electronic components on a substrate and planarizing a first dielectric layer formed over the components. A first insulative hard mask is formed on the first layer and a second dielectric layer on the first hard mask. A first pattern of openings is defined throu

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