Integrated circuit device incorporating DLL circuit

Details Integrated circuit device incorporating DLL circuit Integrated circuit device incorporating DLL circuit

1999-08-27

2003-02-18

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S530000, C327S152000, C327S531000

Reexamination Certificate

active

06522182

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit device incorporating a DLL (Delay Locked Loop) circuit and in particular relates to an integrated circuit device provided with a DLL circuit in which the accuracy of the phase regulation function of the DLL circuit is increased by reducing the effect of power source noise etc. applied through the power source from other circuits within the integrated circuit device.
2. Description of the Related Art
In synchronous integrated circuit devices such as synchronous DRAMs (SDRAMs), the internal circuitry is operated synchronously with a reference clock that is supplied from outside or with the timing of a prescribed phase relationship with the reference clock. For this purpose, they are provided internally with a timing clock generating circuit.
In such a timing clock generating circuit, a DLL circuit is employed in order to eliminate the effect of propagation delay of the reference clock in the integrated circuit device. Specifically, a DLL circuit comprises: a variable delay circuit that outputs a control clock having a prescribed timing by delaying the reference clock, and a phase comparison circuit and delay control circuit that compare the phases of the reference clock and the variable clock that is delayed therefrom, and regulate the amount of delay of the variable delay circuit such that these phases match. The basic layout of such a DLL circuit is shown for example in Laid-Open Japanese Patent Application No. H.10-112182 (laid open: Apr. 28, 1998).
FIG. 1
is a layout diagram of a prior art DLL circuit. In
FIG. 1
, there are shown a DLL circuit
1
, an output circuit
2
and, as an example of a circuit other than a DLL circuit, an input buffer
3
. The power source that is supplied to DLL circuit
1
is constituted by an internal power source Vii
1
that is stepped down from an external power source. This stepped down internal power source Vii
1
is generated by an internal power source system comprising a boosted power source generating circuit
4
that is supplied with external power Vcc and Vss and that generates boosted power Vpp by boosting up power vcc, a control, voltage (gate voltage) generating circuit
5
that generates a gate voltage Vg constituting a control voltage that is controlled to be constant and whose power is supplied by boosted power source Vpp, and an internal power source circuit VR
1
that generates an internal power Vii
1
that is lower by the amount of the threshold voltage of transistor Q
1
from the gate voltage Vg.
In input buffer
3
, there are provided input buffers
11
,
10
that fetche clock CLK and its inverted clock /CLK into the interior from outside, and a dummy input buffer
18
that is utilized as part of the DLL circuit. Clocks /CLK
0
, CLK
0
that are obtained from input buffers
10
,
11
are respectively delayed by passing through variable delay circuits
12
,
13
and are supplied to a data output buffer
14
as control clocks /CLK
1
, CLK
1
controlled to prescribed phases. Data from inside, not shown, is output to the outside as output data Dout in response to these phase-controlled clocks /CLK
1
, CLK
1
. External power sources VccQ, VssQ for the external buffer, different from the ordinary external power sources Vcc and Vss are therefore supplied to this output buffer
14
.
The feedback loop of the DLL circuit is supplied with a clock c-clk obtained by frequency division to a lower frequency by means of frequency divider
15
of internal clock CLK
0
. This reference clock c-clk is supplied as one input of phase comparison circuit
20
. Whereas a variable clock d-i-clk after being delayed by variable delay circuit
16
, dummy data output buffer
17
, and dummy input buffer
18
is supplied to the other input of phase comparison circuit
20
. The result of this phase comparison is supplied to phase control circuit
21
, and phase control circuit
21
regulates the amount of delay of variable delay circuits
12
,
13
,
16
such that the phases of the two input clocks coincide. That is, a common delay control signal N
21
is supplied to these variable delay circuits
12
,
13
,
16
.
Apart from the above output buffer, the control clock is sometimes supplied to other prescribed internal circuitry so that the operating timings of this internal circuitry can be controlled. For example, the control clock may be supplied to an input buffer.
As described above, in the DLL circuit according to the prior art example, internal power source Vii
1
for the DLL circuit is generated by an internal power source circuit VR
1
exclusively for the DLL circuit
1
, in order to avoid the effect of power source noise from the rest of the circuits. To circuits other than the DLL circuit
1
, such as input buffer
3
, external power source Vcc is supplied, or internal power source Vii
2
from internal power source circuit VR
2
, which is different from internal power source circuit VR
1
which is exclusively for the DLL circuit
1
is supplied. Also, to output circuit
2
, which requires large current, external power sources VccQ, VssQ for the output circuit
2
, which are different from the ordinary external power sources Vcc and Vss are supplied. Also, to DLL circuit
1
, circuit
3
other than DLL circuit and power source systems
4
,
5
, externally earthed power source Vss is supplied.
However, the internal power source Vii
1
that is stepped down in voltage and that drives the DLL circuit
1
is supplied to all the constituent elements of the DLL circuit
1
. Consequently, power source noise is generated in internal power source Vii
1
by the operation of each of the constituent elements of the DLL circuit. Thus, the power source noise generated by operation of some constituent elements of the DLL circuit affects the operation of other constituent elements. For example, when the inverted clock /CLK
1
passes through the variable delay circuit
12
, power source noise is produced in internal power source Vii
1
by the operation of variable delay circuit
12
with the result that the amount of delay of other variable delay circuits
13
,
16
that are driven by the same internal power source Vii
1
fluctuates because of the effect of this power source noise. As a result, jitter (variation of phase) of the control clock is caused, making precise phase regulation difficult.
More specifically, when the reference clock c-clk and the variable clock d-i-clk passed through variable delay circuit
16
and dummy delay circuits
17
,
18
go into the lock-on condition, power source noise is generated in internal power source Vii
1
by the action of the other variable delay circuits
12
,
13
; this affects the operation of the variable delay circuit
16
in the feedback loop referred to above, causing its delay amount to change and in some cases may produce an unlocked condition. When this happens, even though the external clocks CLK, /CLK and control clocks CLK
1
, /CLK
1
are in the lock-on condition, they are put into the unlocked condition by power source noise; this therefore results in jitter of the control clocks CLK
1
and /CLK
1
, causing inaccurate timing of the output of data output Dout.
Also, as another example, phase comparison circuit
20
is provided with a phase coincidence detection unit for detecting whether or not the phase difference between the input clocks c-clk and d-i-clk is in the lock-on condition. In some cases, this phase coincidence detection unit, due to the effects of power source noise produced by the operation of variable delay circuits, detects the unlocked condition irrespective of the lock-on condition. In this case also, the delay control circuit
21
controls the amount of delay of variable delay circuit
16
in accordance with this phase comparison result and tries to achieve the lock-on condition, but at this point the effect of power source noise disappears so unlocking in respect of the variable clock d-i-clk after alteration of this delay amount is now detected, so delay control circuit
21
again contr

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