Integrated circuit device including a circuit to generate...

Details Integrated circuit device including a circuit to generate... Integrated circuit device including a circuit to generate...

2011-07-19

2011-07-19

Alphonse, Fritz (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S800000, C714S758000

Reexamination Certificate

active

07984363

ABSTRACT:
An integrated circuit device includes a plurality of memory circuits, a memory hibernation state control circuit to bring the memory circuits into a hibernation state in response to an external command, a state controller which indicates an interrupt in a memory circuit in a hibernation state, and a plurality of partial error checking and correcting (ECC) code generating circuits which are provided for the memory circuits, respectively, to code hold data of an address of a memory circuit in a hibernation state in accordance with a rule of a Hamming code determinant by an interrupt in the memory circuit in the hibernation state. The integrated circuit device further includes a code storage memory which obtains ECC code data corresponding to all of the hold data based on partial ECC codes coded by the partial ECC code generating circuit and stores the ECC code data in a corresponding address.

REFERENCES:
patent: 6167548 (2000-12-01), Yamakura
patent: 6185718 (2001-02-01), Dell et al.
patent: 6546489 (2003-04-01), Frank et al.
patent: 6662333 (2003-12-01), Zhang et al.
patent: 6829722 (2004-12-01), Lin
patent: 7620784 (2009-11-01), Panabaker
patent: 2001-249854 (2001-09-01), None

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