Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2000-09-20
2003-11-04
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S400000
Reexamination Certificate
active
06643792
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-211685, filed Jul. 12, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a large-scale integrated circuit device (to be referred to as an LSI hereinafter) having a clock frequency changing function and a computer system using the large-scale integrated circuit and a clock frequency changing method.
In a conventional LSI operated with a clock, in order to secure the operation under a high frequency, any one of the following three methods is employed:
I. method for supposing the worst conditions in design to determine a clock frequency;
II. method for selecting a chip operated at a high frequency in inspection after manufacturing;
III. method for attaching a sensor for measuring the temperature of an LSI in operation and for controlling an operation frequency with software to decrease the operation frequency when the LSI temperature raises over a predetermined temperature.
The method I is applied to a relatively small number of products such as ASIC (Application Specific Integrated Circuit) for specific applications.
The method II is frequently applied to a large number of products such as general-purpose memories and microprocessors.
The method III is used as a method for preventing a timing error by decreasing an operation frequency when an LSI cannot be cooled even though a cooling fan or the like is used in a notebook type personal computer or the like.
In the prior art, for example, design conditions are too severe in the method I, and an LSI is operated at a frequency lower than an upper limit of the operable frequency. As a result, the LSI must be used with operation performance lower than the actual capability (maximum value of an operation frequency).
The design conditions in the method II are milder than those in the method I. However, conditions such as a peripheral temperature and a power supply voltage are often severer than the real usage conditions, and an LSI must be used in a state in which operation performance is lower than the actual operation performance.
Even in the method III, although the peripheral temperature is considered, conditions such as a power supply voltage are often severer than the real usage conditions, and an LSI must be used in a state in which operation performance is lower than the actual operation performance.
In the conventional technique described above, in general, the practical maximum operation frequency of an LSI is fixedly determined every product within a range of performance lower than the maximum performance of the LSI.
On the other hand, as described in U.S. Pat. No. 5,872,907, the following technique is also proposed. That is, when an error caused by an AC timing error is detected in a fault tolerant type computer, a clock frequency is changed (decreased) to improve the reliability of the system.
In some personal computer or the like, a mechanism for multiplying an operation frequency of a processor or the like with a base clock of a system bus or the like by setting a register may be incorporated. In the mechanism of this type, a clock frequency is changed by using interruption while the system is operated in a stable condition.
According to the clock frequency changing technique, a computer (more-specifically, LSI) can be operated to achieve the actual capability of the computer (LSI). For this reason, the technique is useful to solve the problems. However, in an actual operation state, in order to stably operate the LSI to achieve the maximum performance, the clock frequency changing technique is not always sufficient.
Therefore, the present inventor proposes “Clock Generation Circuit and Clock Generation Method” which can changes a clock frequency in Japanese Patent Application No. 11-318771 (unpublished), so that an LSI to which the clock generation circuit (or the clock generation method) is applied is stably operated to achieve the maximum performance in an actual operation state.
However, in any clock frequency changing technique, a device for dynamically changing a clock frequency in a system operation in synchronism with another LSI (clock generation circuit included therein) is not considered.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an integrated circuit device having a clock frequency changing function which can dynamically change the frequency of a clock generated by the integrated circuit device in synchronism with another integrated circuit device, and a computer system having the integrated circuit device and a clock frequency changing method.
According to the present invention, there is provided an LSI which incorporates a clock generation circuit which can change a clock frequency, which is connected to a system bus and a clock control bus independent of the system bus together with another LSI, which operates in synchronous with the other LSI by the clock generated by the incorporated clock generation circuit, and which has a clock frequency changing function, including clock frequency changing means which dynamically executes changing of a clock frequency of the incorporated clock generation circuit by using at least the clock control bus in synchronism with another LSI.
When a computer system is configured such that a plurality of LSIs each having the above configuration are connected to the system bus and the clock control bus, by using the clock control bus for changing a clock frequency of every LSI, the clock frequency can be dynamically changed during system operation in synchronism with each other.
In order to change a clock frequency by using the clock control bus, at least the following two signals, i.e., a first signal representing that the clock frequency must be changed in a predetermined direction and a second signal representing that the clock frequency is changed in a direction opposing the direction of the first signal or that the clock frequency need not be changed are flowed through the clock control bus, and the clock frequency changing means includes clock state determination means for operating the first and second signals such that a present clock state can be designated, so that the clock frequency may be changed on the basis of the clock state designated by the first and second signals. When the clock state is represented by only the first and second signals, by a specific combination of the first signal representing that the change of the clock frequency is not unnecessary and the second signal representing that the clock frequency need not be changed in the predetermined direction, a clock state in which the clock frequency must be changed in the direction opposing the predetermined direction may be indicated. In addition, a third signal representing that the clock frequency must be changed in the direction opposing the predetermined direction may be added.
The system bus may also be used to change the clock frequency, and the clock frequency may be synchronously changed by using a bus transaction on the system bus. When the bus transaction on the system bus is used, a relatively high-speed clock can be controlled depending on the performance of the system bus.
In order to change the clock frequency by using the bus transaction on the system bus, the clock frequency changing means for an LSI serving as a master for a clock frequency changing operation using the bus transaction comprises:
means for detecting that a clock state which is represented by at least the first and second signals and which designates that a clock frequency must be changed is continued for a first number of clock cycles;
means for issuing the bus transaction for clock frequency changing to a target LSI of LSIs on the system bus and the clock control bus depending on the detection result of the detecting means; and
timing adjustment means for waiting until a second number of clock cycles elapse after a normal comple
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Heckler Thomas M.
Kabushiki Kaisha Toshiba
LandOfFree
Integrated circuit device having clock frequency changing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit device having clock frequency changing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit device having clock frequency changing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3141260