Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-08-17
2001-08-14
Clark, Jhihan B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S752000, C257S759000
Reexamination Certificate
active
06274933
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits, and, more particularly, to integrated circuits having interlevel dielectric layers.
BACKGROUND OF THE INVENTION
To accommodate higher packing density in present integrated circuits, metal connection to integrated circuit devices formed in a semiconductor substrate are made by multilayer interconnects. Each level of multilayer interconnects is supported over the semiconductor substrate by an interlevel dielectric. Generally, the integrated circuit structure includes a dielectric layer and metal lines are laid down in parallel strips on top of the dielectric layer. Additional levels of multilayer interconnects are formed over this dielectric layer each including additional metal interconnects and an interlevel dielectric layer.
A number of methods for depositing dielectric materials by chemical vapor deposition (CVD) are currently available. For gap fill applications, CVD methods have their advantages. They are well-known processes, and they generally require a smaller number of overall steps than spin-on methods. For damascene processes, blanket deposition is all that is required for interlevel layers, and that can be done with either a CVD or a spin-on process. Pre-metal dielectric (PMD) and shallow-trench isolation (STI) require effective gap fill capability whether damascene is used or not. For STI, high-aspect ratio (e.g. 4:1) trenches must be filled with high-quality dielectric material.
One process for dielectric gap fill applications is high-density plasma CVD (HDP-CVD). HDP-CVD films are dry, compressive films that lend themselves well to multiple metal layer applications such as microprocessors. Since it is a plasma-based system, a typical HDP system would cost more than a tetra-exthyl oxysilane-ozone (TEOS/O
3
) system, but it provides the throughput advantages of requiring fewer process steps. TEOS-ozone is used in many DRAM applications, since the market is more cost sensitive, and TEOS-ozone equipment costs less. TEOS-ozone films, as others that depend on a flow mechanism, must be annealed, which adds steps and increases production time.
The HDP-CVD oxide deposition process is actually a deposition-etchback process, where both are performed simultaneously. The plasma is a high-density mixture containing oxygen and argon. A DC bias pulls oxygen to the wafer surface where it reacts with silane (SiH
4
) to form SiO
2
. The argon simultaneously sputters deposited material away. The etchback is designed to remove overhang of the deposited material at the top of the gap. Although much of the deposited material is removed, it provides a time savings over some other methods since no anneal is required.
HDP-CVD was originally developed for interlevel dielectric (ILD) applications, but it also deposits high-quality material for STI, PMD and nitride etch-stop applications. Also, with the removal of the sputtering component of the plasma, it becomes a PECVD capping layer tool to prepare for chemical mechanical polishing (CMP). The etch:deposition (E:D) ratio, is usually kept somewhere between 0.14 and 0.33, and is controlled by the ratio of the gases, the chamber pressure, the ion-to-neutral flux ratio, the ion energy and the rf bias on the substrate.
HDP-CVD is used for depositing fluorosilicate glass (FSG), a low dielectric constant (low-k) dielectric. Low-k dielectrics reduce capacitive coupling between adjacent metal layers. Furthermore, an ideal low-k dielectric offers low-k as well as low leakage, low thermal coeffcient of expansion, high dielectric breakdown voltage, low water absorption, for example. FSG layers, which are a silicon oxyfluoride (F
x
SiO
y
), are known to have a dielectric constant of about 3.2-3.6, depending on the fluorine concentration. The high electronegativity of fluorine reduces the polarizability of the film, decreasing its dielectric constant. FSG layers are formed by adding silicon tetrafluoride (SiF
4
) to the silane (SiH
4
), O
2
and argon gases. HDP-CVD of FSG layers is relatively time consuming and expensive.
Chemical-mechanical polishing (CMP) is employed to planarize layers deposited on semiconductor wafers. Chemical mechanical polishing involves holding and rotating a semiconductor wafer against a wetted polishing platen under controlled chemical, pressure and temperature conditions. Typically a slurry solution is used as the abrasive fluid. The polishing mechanism is a combination of mechanical action and the chemical reaction of the material being polished with the slurry solution.
U.S. Pat. No. 5,807,785 to Ravi, for example, discloses a sandwich silicon dioxide layer for filling gaps in the metal layers on a semiconductor substrate. A first layer is formed by plasma-enhanced CVD (PECVD) and a second layer is formed by sub-atomic CVD (SACVD) to achieve a low dielectric constant. Also, U.S. Pat. No. 5,759,906 to Lou discloses a planarization method for dielectric layers using a multilayer of spin-on glass (SOG) which is deposited and baked after the deposition of each layer.
There is a need for a planarized low-k interlevel dielectric layer including an HDP-CVD FSG layer which is more cost effective and substantially decreases the risk of exposing the metal in the conductive layers to potential fluorine attack.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the invention to provide an integrated circuit device having a planarized low-k interlevel dielectric layer including an HDP-CVD FSG layer which protects the conductive layers from fluorine exposure.
This and other objects, features and advantages in accordance with the present invention are provided by an integrated circuit device comprising a first metal layer adjacent a semiconductor substrate, the first metal layer including a plurality of patterned metal lines having gaps therebetween, and at least some of the plurality of patterned metal lines having different widths. The device further includes a composite dielectric layer comprising a fluoro-silicate glass (FSG) layer over the plurality of patterned metal lines and filling the gaps between the plurality of patterned metal lines, and a planar undoped oxide layer on the FSG layer. A second metal layer may be adjacent the planar undoped oxide layer. The FSG layer has a plurality of peaks each of which is above one of the plurality of patterned metal lines and each of which has substantially a same height above the first metal layer to protect the second metal layer from exposure to fluorine from the FSG layer.
The device may also include a protective dielectric layer on the patterned metal lines, and the undoped oxide layer may comprise an undoped-silicate glass (USG). The first metal layer may comprise at least one of aluminum and copper and the FSG layer preferably has a thickness of at least 100 nanometers higher than the thickness of the first metal layer.
REFERENCES:
patent: 5578531 (1996-11-01), Kodera et al.
patent: 5759906 (1998-06-01), Lou
patent: 5807785 (1998-09-01), Ravi
patent: 5876798 (1999-03-01), Vassiliev
patent: 5877080 (1999-03-01), Aoi et al.
patent: 6008120 (1999-12-01), Lee
patent: 6071830 (2000-06-01), Matsuzawa et al.
patent: 09 219448 (1997-08-01), None
patent: 2 313 954 (1997-12-01), None
patent: 8-111395 (1996-04-01), None
Patent Abstracts of Japan, vol. 1996, No. 08, Aug. 30, 1996 & JP 08 111395 A (Sony Corp), Apr. 30 1996 *abstract; figures 1,2*.
Abdelgadir Mahjoub Ali
Maury Alvaro
Agere Systems Guardian Corp.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Clark Jhihan B
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