Integrated circuit device, electronic equipment, and method...

Details Integrated circuit device, electronic equipment, and method... Integrated circuit device, electronic equipment, and method...

2002-05-10

2004-03-16

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S041000, C716S030000

Reexamination Certificate

active

06707314

ABSTRACT:

Japanese patent application no. 2001-141998 filed on May 11, 2001 is hereby incorporated by reference in its entirety.
BACKGROUND
The present invention relates to an integrated circuit device, electronic equipment, and a method of placing (layout) an integrated circuit device.
The universal serial bus (USB) standard has recently attracted attention as an interface standard for connections between personal computers and peripheral equipment (broadly speaking: electronic equipment). This USB standard has the advantage of enabling the use of connectors of the same standard to connect peripheral equipment such as a mouse, keyboard, and printer, which are connected by connectors of different standards in the prior art, and of enabling the implementation of plug-and-play and hot-plug features.
In comparison with the IEEE 1394 standard, which is also attracting notice as a standard for the same serial bus interface, this USB standard has a problem in that the transfer speed thereof is slower.
In this case, attention is focussed on the decision to use the USB 2.0 standard which can implement a data transfer speed of 480 Mbps (in HS mode), far faster than that of the previous USB 1.1 standard, while maintaining backward compatibility with USB 1.1. The USB 2.0 transceiver macrocell interface (UTMI), which has defined interface specifications for parts of the physical-layer and a logical-layer circuit under USB 2.0, has also been proposed.
In addition to the full-speed (FS) mode defined by the prior-art USB 1.1, USB 2.0 has provided a transfer mode called high-speed (HS) mode. Since data transfer in this HS mode is at 480 Mbps, this enables the implementation of data transfer at a much higher speed than the data transfer at 12 Mbps of FS mode. This USB 2.0 therefore makes it possible to provide an interface that is optimal for storage devices such as hard disk drives and optical disk drives that require fast transfer speeds.
With USB 2.0, however, it is necessary to send and receive small-amplitude signals at far higher speeds than those under USB 1.1. The physical-layer circuit that processes such small-amplitude signals is therefore required to have a high level of sophistication, and it is desirable with UTMI-standard macrocells (megacells or macro blocks) including such a physical-layer circuit that the cell placement and routing should be done manually.
An integrated circuit device including a UTMI-standard macrocell, on the other hand, is combined with a logical-layer circuit such as that for a serial interface engine (SIE) or user-specified logic, which means that the configuration and scale of this logical-layer circuit will vary depending on the user of the integrated circuit device. When designing and fabricating an integrated circuit device including such a macrocell, a technical problem is to respond to diverse user demands while maintaining the high level of sophistication of the physical-layer circuit.
SUMMARY
An integrated circuit device in accordance with one aspect of the present invention relates to an integrated circuit device including a plurality of macrocells, the integrated circuit device comprising:
a first macrocell which includes at least a physical-layer circuit conforming to a given interface standard for performing data transfer through a bus and; and
a second macrocell which includes a circuit in an upper layer of the physical layer,
wherein the first macrocell is placed in such a manner that a corner portion of the first macrocell that is a portion at which first and second sides of the first macrocell intersect is positioned at a corner portion of the integrated circuit device.


REFERENCES:
patent: 6150837 (2000-11-01), Beal et al.
patent: A 2000-138292 (2000-05-01), None
patent: A 2000-148716 (2000-05-01), None

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