Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-05-05
2004-03-02
Jones, Hugh (Department: 2123)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S006000
Reexamination Certificate
active
06701502
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an arrangement/wiring method and an arrangement/wiring apparatus for automatically designing layout patterns of an integrated circuit device, and to a recording medium which stores a program for making a computer execute the arrangement/wiring procedure.
As a conventional arrangement/wiring method of automatically designing layout patterns of an integrated circuit device, the minimization of the chip area after the arrangement/wiring or so called compaction is available.
FIG. 5
is a block diagram illustrating a conventional automatic arrangement/wiring apparatus for designing layout patterns. This apparatus comprises an entering unit
1
for entering instructions for cell arrangement or the like, a cell arrangement unit
2
, a net list
3
which contains information on the connection of the logical circuit, and layout information
4
which contains physical information of cells to be arranged. The cell arrangement unit
2
arranges the cells which compose the logical circuit, using the net list
3
and the layout information
4
in response to the directions of the entering unit
1
. The apparatus further comprises a channel generation unit
5
for determining the wiring area for each of the signal lines which connect the arranged cells, a global/minute wiring unit
6
for determining the wiring path for each of the signal lines in the wiring area and then wiring the signal lines, a compaction execution unit
7
for minimizing the chip area while fulfilling design rules
8
after the wiring of the global/minute wiring unit
6
, and a display unit
10
for displaying the contents of an arrangement/wiring process, a compaction process, and the like.
The operation of the automatic arrangement/wiring apparatus thus constructed will be described as follows with reference to the flowchart shown in FIG.
6
.
In step S
1
, the name of a signal line to be wired is entered based on the net list
3
which contains the information on the connection of the logical circuit and the layout information
4
which contains the physical information of the cells. In step S
2
, the cells are arranged either automatically or manually. In step S
3
, the wiring area for each of the signal lines which connect the cells is determined. This is referred to as channel generation. Generally, the area which is not involved in arranging the cells is assigned to the wiring area; however, there are cases where the wiring area can be set up on the cells, or a wiring prohibition area is set up. In step
4
, the wiring paths for the signal lines which connect the terminals of the cells are roughly determined with reference to the entered net list
3
. This is referred to as global wiring. Here, the wiring is conducted by assigning higher priorities to such signal lines that might cause remarkable inconvenience when they have long wiring lengths. To be more specific, signal lines with highest priorities are generally wired automatically so as to have the minimum wiring length and optimum timing. In the meantime, the paths for such specific signal lines as for a power source, ground, clock, and the like are usually wired manually.
In step S
5
, minute wiring including the determination of wiring positions in each channel is carried out. In the compaction process at step S
6
, the wiring is modified by hand so as to make the chip area as small as possible while fulfilling the design rules, and the process is terminated.
By means of the compaction process for minimizing the chip area, the designer repeats the modification of the wiring, so that the integration of the circuit gradually increases and the chip area decreases. As a result, it becomes possible to design an integrated circuit device with higher integration.
However, in the above-described compaction process, there is a limit to the repeated modification of the wiring by the designer. Furthermore, to prolong the time required for the compaction process for reducing the chip area goes against the demand for putting good products on the market as soon as possible.
In order to solve these problems, it is necessary to determine the completion of the compaction process, and it is possible to use the decrease rate of the chip area in each compaction process as a method of determining the completion. According to this method, as shown in
FIG. 7
, every time the compaction process is completed, the chip area Sn before the process and the chip area Sn+
1
after the process are compared, then the decrease rate of the chip area (Sn−Sn
+1
)/Sn (n is the number of times of the compaction process) is compared with a specified value. To be more specific, when the decrease rate of the chip area is larger than the specified value, another compaction process is conducted, and when the decrease rate of the chip area is smaller than the specified value, the compaction process is terminated.
However, there is a problem that in spite of the provision of such standards for determining the completion time of the compaction process, the chip area of an integrated circuit device when its layout is finally designed differs depending on the difference in the level of the skills of designers.
To be more specific, since layout designers having different levels of technical skill conduct different wiring modification, the chip area after the completion of the process might greatly differ even under the same conditions.
FIG. 8
is a graph showing the change in the chip area S along with the designing time (or number of times) in the cases of a skilled designer and an unskilled designer. In this graph, the curve A indicates the case of the unskilled designer and the curve B indicates the cases of the skilled designer. Since the decrease rate of the chip area S becomes lower than the specified value on both the curves A and B when the fifth compaction process is completed, the compaction process is terminated at that moment. However, the difference in the final chip area S between the curves A and B is obvious.
As described hereinbefore, there is a problem that the different levels of the skill of designers cause different integration degrees of an integrated circuit device.
SUMMARY OF THE INVENTION
The object of the present invention is to provide an arrangement/wiring method and arrangement/wiring apparatus for performing optimum arrangement/wiring regardless of the level of the skill of a designer, by establishing standards for objectively determining the completion of a compaction process, and also to provide a recording medium which stores the optimum arrangement/wiring procedure and an integrated circuit device which is produced in accordance with the arrangement/wiring method.
In order to achieve the above object, the present invention has a feature that the compaction process for minimizing the chip area while fulfilling the design rules is terminated when the number of elements per unit area exceeds a predetermined setting value.
The arrangement/wiring method of an integrated circuit device of the present invention is an arrangement/wiring method of an integrated circuit device for arranging cells each containing at least one element and wiring signal lines which connect the cells in the integrated circuit device comprising the steps of: performing a compaction process so as to reduce a chip area of the integrated circuit device in which the cells have been arranged and the signal lines have been wired while fulfilling design rules; obtaining the standard value of element density which is previously stored in a storage means and indicates the number of elements per unit area, and comparing the standard value with the element density of the integrated circuit device to which the compaction process has been executed; and ordering that the compaction process is repeated when the element density is smaller than the standard value, and ordering that the compaction process is terminated when the element density is larger than the standard value.
According to this method, the completion of the compaction proce
Kondo Atsuo
Kuroda Takao
Jones Hugh
McDermott & Will & Emery
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