Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated – With specified encapsulant
Reexamination Certificate
1999-01-12
2002-03-12
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
With specified encapsulant
C257S707000, C257S706000, C257S685000, C257S723000, C257S687000, C257S788000, C257S787000, C257S796000, C257S684000, C257S646000, C257S675000, C257S712000, C257S905000, C365S230030, C365S230060, C365S233100, C365S194000, C365S203000, C711S167000, C361S704000
Reexamination Certificate
active
06355985
ABSTRACT:
TECHNICAL FIELD
The present invention relates to integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device.
BACKGROUND OF THE INVENTION
Personal computers have experienced expansive growth and improvements in technology in recent decades. Improvements in processing technologies have enabled fabrication of computer components having reduced feature sizes. Such reduction in feature sizes has also enabled the fabrication of smaller components with increased capabilities.
For example, both the operational speeds of processing devices and the capacity to store data of memory devices have been significantly increased. However, there exists a desire to increase the storage capacity of conventional memory devices. Data is stored in components comprising random access memory (RAM) in some conventional configurations. Exemplary random access memory devices include static random access memory (SRAM) and dynamic random access memory (DRAM). It has been desired to increase the speed of memory devices to increase the overall performance of the conventional computer systems.
Synchronous-link dynamic random access memory (SLDRAM) devices have been introduced to provide faster electronic storage devices. The synchronous-link dynamic random access memory devices provide benefits of very high speed (e.g., 400 megahertz data rate) and very high bandwidth (e.g., 800 Mb/s I/O bandwidth). In addition, such storage devices can provide pipelined or concurrent operation. Exemplary synchronous-link dynamic random access memory devices provide synchronous and packet oriented operation with storage capabilities in excess of 75 MB.
Various packaging configurations have been utilized as housings for conventional synchronous-link dynamic random access memory devices. Exemplary configurations include vertical surface mounted packages (VSMP) and horizontal surface mounted packages (HSMP). In typical configurations, the leads extend from one surface of the mounted packages and are bent and trimmed for the desired orientation.
It has been observed that conventional synchronous-link dynamic random access memory devices produce a considerable amount of heat. Accordingly, various structures have been utilized to reduce or dissipate the generated heat. One prior art technique has considered the utilization of a heat sink bonded to an external wall of a package which houses the synchronous-link dynamic random access memory semiconductor die. In such conventional designs, an epoxy or other adhesive is typically utilized to bond or otherwise adhere the heat sink to the external surface of the housing package. Drawbacks are presented by the conventional designs inasmuch as subsequent processing of an individual synchronous-link dynamic random access memory device often results in heating the memory device to the point of failure of the epoxy heat sink bond.
Therefore, there exists a need to provide improved memory configurations to overcome the shortcomings experienced within the prior art devices.
SUMMARY OF THE INVENTION
The present invention includes integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device.
According to one aspect of the present invention, an integrated circuit device includes a semiconductor die and a first housing encapsulating the semiconductor die. A heat sink is positioned proximate the first housing. A second housing is formed to encapsulate at least a portion of the heat sink. The heat sink is preferably thermally coupled with the semiconductor die and configured to dissipate or expel heat therefrom. The second housing is configured to encapsulate both the heat sink and the first housing in certain aspects of the invention.
Another aspect of the present invention provides an integrated circuit device which includes a first housing formed about a semiconductor die and at least portions of a plurality of leads electrically coupled with the semiconductor die. A heat sink is thermally coupled with the first housing. A second housing is formed about the heat sink and at least a portion of the first housing.
The present invention additionally provides methods of forming an integrated circuit device. One aspect provides a method including the steps of providing a semiconductor die and forming a first housing about the semiconductor die. The method also includes thermally coupling a heat sink with the first housing and forming a second housing about at least a portion of the heat sink following the thermally coupling.
The present invention also provides additional structure and methodology aspects.
REFERENCES:
patent: 5057457 (1991-10-01), Miyahara et al.
patent: 5249101 (1993-09-01), Frey et al.
patent: 5331205 (1994-07-01), Primeaux
patent: 5352851 (1994-10-01), Wallace et al.
patent: 5379186 (1995-01-01), Gold et al.
patent: 5406117 (1995-04-01), Dlugockecki et al.
patent: 5698899 (1997-12-01), Hirakawa et al.
patent: 5789813 (1998-08-01), Kirkland et al.
patent: 5847467 (1998-12-01), Wills et al.
patent: 5864175 (1999-01-01), Burns
patent: 5946556 (1999-08-01), Hashiznme
patent: 6104093 (2000-08-01), Coletka et al.
patent: 6144107 (2000-11-01), Narita
patent: 57-133653 (1982-08-01), None
patent: 63-141353 (1988-06-01), None
IEEE 100 The Authoritatve Dictionary of IEEE Standards Terms-Seventh Edition (2000) p. 510.
Pecht, Michael, editor; “Handbook of Electronic Package Design”; p. 95-97, 219-220.
Seraphim, Donald P., editor; “Principles of electronics Packaging”; p. 130-131, 600.
How to Make IC Package, Internet Web pages from www.msato@iis.u0tokyo.ac.jp web site, Aug. 31, 1998, 10 pages.
SLD4M18DR400 4 Meg × 18 SLDRAM, Internet Web pages from www.sldram.com web site, 1998, 12 pages.
Micro)n Technology, Inc.
Wells, St. John, Roberts Gregory & Matkin P.S.
Williams Alexander O.
LandOfFree
Integrated circuit device and synchronous-link dynamic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit device and synchronous-link dynamic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit device and synchronous-link dynamic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2839720