Integrated circuit device and method therefor

Details Integrated circuit device and method therefor Integrated circuit device and method therefor

2002-03-19

2004-06-22

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S696000

Reexamination Certificate

active

06753242

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits and more particularly to integrated circuits with a recess in the substrate.
RELATED ART
In the manufacture of integrated circuits one of the problems that has become more significant as dimensions have become smaller is recesses in the substrate that occur under normal processing. The recesses in the substrate occur primarily as a consequence of the substrate being exposed during the etching away of some portion of a layer of material that was over the substrate. An etchant is applied to the substrate for some amount of time during and/or after the layer that is being etched has been removed. One example is that there is a situation in which there is exposed substrate at the onset of an etch of another material in a different location. Another example is that a thin layer over the substrate is etched through during an etch of a material elsewhere so that the substrate becomes exposed part way through the etch of the material elsewhere. Another example is that a layer over the substrate is being etched and after the substrate becomes exposed, the etch continues as an over-etch to ensure that the layer that is desired to be removed is completely removed. The etchant that is chosen desirably does not significantly etch semiconductor substrates, but as a practical matter such etchants are very difficult to work with. Consequently the layers that are desired to be removed are removed by an etchant that does have some etching effect on the semiconductor substrate, typically silicon. Such a process is shown in
FIGS. 1-9
.
Shown in
FIG. 1
is a semiconductor device
10
useful in making an integrated circuit comprising a substrate
12
, a polysilicon gate
14
, an anti-reflective coating (ARC)
16
of nitride, and a thin oxide
18
which is between gate
14
and substrate
12
as well as extending in areas adjacent to gate
14
. In order to remove nitride ARC
16
, an etchant, such as a halogen based material such as fluorine and chlorine, is used. These etchants also etch silicon although at not as fast a rate as nitride is etched. The result of removing ARC
16
is a recess surface
22
shown in FIG.
2
. Shown in
FIG. 3
is device
10
after formation of a sidewall spacer
24
. Sidewall spacer
24
is formed of oxide and occurs as a result, as is commonly known, of applying a relatively conformal layer and subsequently etching it with an anisotropic etch. This causes a further recess in substrate
12
aligned with sidewall spacer
24
. Shown in
FIG. 4
is formation of source/drain region
26
and source/drain
28
using sidewall spacer
24
as a mask. This implant is commonly called the extension implant and has a relatively lower doping concentration than a subsequent heavy source/drain implant.
Shown in
FIG. 5
is device
10
after deposition of an oxide liner
30
and a nitride layer
32
. Nitride layer
32
is then etched back as is liner
30
resulting in sidewall spacer
34
and liner portion
38
. During this processing, source/drain regions
26
and
28
diffuse, expanding the area of source/drain regions
26
and
28
. Shown in
FIG. 7
is device
10
after a heavy implant to form heavily-doped regions
40
and
42
using sidewall spacer
34
as a mask. Shown in
FIG. 8
is continued expansion of source/drain regions
26
and
28
as well as diffusion of regions
40
and
42
due to standard processing.
Shown in
FIG. 9
is device
10
after formation of silicide regions
48
and
50
which extend under regions
40
and
42
. This also shows a completed diffusion of regions
49
and
51
, which are the remaining portions of regions
26
and
28
. These regions may not extend all the way to gate oxide
20
. With the regions
49
and
51
not fully extending to be in contact with gate oxide
20
, there is some additional space between gate
44
and the channel formed between regions
49
and
51
so that current passing between regions
49
and
51
is less than it would be if they had diffused in closer proximity to gate
20
. This is a disadvantage and is a direct result of the additional distance the diffusion must travel due to the recess of substrate
12
adjacent to gate
44
. Silicide region
46
is also formed on top of gate
14
and consumes a significant amount of gate
14
to leave a gate that is a combination of a region
44
of polysilicon and a region
46
of silicide.
Thus, there is a need to reduce the adverse effects of a recess that occurs in the substrate during normal processing. This problem continues to get worse as dimensions decrease and voltages decrease. The ability to completely invert the channel and provide optimum current between source and drain is compromised if the source and drain do not have the proper overlap with the overlying gate.


REFERENCES:
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patent: 5960270 (1999-09-01), Misra et al.
patent: 5972762 (1999-10-01), Wu
patent: 6066567 (2000-05-01), En
patent: 6087271 (2000-07-01), En
patent: 6156126 (2000-12-01), Chen et al.
patent: 6245682 (2001-06-01), Fu
patent: 6368947 (2002-04-01), Yu
patent: 6372589 (2002-04-01), Yu
patent: WO01/50504 (2001-07-01), None
PCT International Search Report.

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