Integrated circuit device

Details Integrated circuit device Integrated circuit device

2002-07-05

2004-04-27

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S349000, C257S351000, C257S353000, C257S354000, C257S616000, C257S018000

Reexamination Certificate

active

06727550

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an integrated circuit device and more particularly to an integrated circuit device including field effect transistors.
2. Description of the Related Art
An attempt has been made to enhance the operation speed, improve the functions and lower the power consumption of large-scale integrated circuits (LSI) such as microprocessors. In order to successfully achieve the above attempt, it is necessary to make transistors small while the driving abilities of the respective transistors configuring the circuit are maintained or enhanced. In order to meet the above requirement of miniaturization, the gate length is reduced in the conventional MOSFET, for example.
However, recently, a technical or economical barrier to a reduction in the gate length rapidly becomes higher. Therefore, as a method for enhancing the operation speed of the LSI, a method of using a channel material with high mobility is known other than the method for reducing the gate length.
As the channel material with high mobility, much attention is paid to strained Si and strained SiGe. The method for forming strained Si or strained SiGe is as follows. Strained Si is formed by forming Si on lattice relaxed SiGe having a larger lattice constant than Si by epitaxial growth. Strained SiGe is formed by forming strained SiGe on lattice relaxed SiGe or Si having a lower composition ratio than strained SiGe by epitaxial growth. The mobility of electrons and holes in strained Si is increased by in-plane tensile strain and the mobility of holes in strained SiGe is increased by in-plane compressive strain. Further, since the amount of strain caused in the channel layer becomes larger as a difference in the Ge composition ratio between the underlying lattice relaxed SiGe layer and the channel material is larger, that is, a difference in the lattice constant therebetween is larger, the mobility becomes higher.
The inventor of this application and others have proposed a MOSFET (strained SOI-MOSFET) having an SOI (Si-on-insulator) structure combined with strained Si and relaxed SiGe and demonstrated the operation thereof (see T. Mizuno, S. Takagi, N. Sugiyama, J. Koga, T. Tezuka, K. Usuda, T. Hatakeyama, A. Kurobe, and A. Toriumi, IEDM Technical Digests p. 934 (1999), the entire contents of which are incorporated herein by reference).
FIG. 1
is a cross sectional view showing a strained SOI-MOSFET using strained Si.
As shown in
FIG. 1
, the strained SOI-MOSFET includes an Si substrate
6
, an insulation layer
5
formed on the Si substrate
6
, a lattice relaxed Si
0.9
Ge
0.1
buffer layer
4
formed on the insulation layer
5
, a strained Si layer
3
formed on the lattice relaxed Si
0.9
Ge
0.1
buffer layer
4
, a gate oxide layer
2
formed on the strained Si layer
3
, and a gate electrode
1
formed on the gate oxide layer
2
. A portion of the strained Si layer
3
which lies under the gate oxide layer
2
functions as a channel region. Source/drain regions
7
are formed on both sides of the channel region. The strained Si layer
3
may be replaced by a strained SiGe layer.
The strained SOI-MOSFET with the above structure has an advantage that the carrier mobility is high since the strained Si layer
3
is used as the channel. Further, in addition to the above advantage, it has advantages that the junction capacitance can be made small by use of the SOI structure and the MOSFET can be made small with the impurity concentration kept low. Since holes generated by impact ionization can be easily absorbed into the source region through the relaxed SiGe layer, occurrence of the body floating effect which is normally treated as a problem in the SOI structure can be suppressed.
The inventor of this application and others have found that it is necessary to substantially completely lattice-relax the lattice relaxed Si
1−x
Ge
x
buffer layer
4
with lower dislocation density and make the thickness thereof to 30 nm or less in order to put the strained SOI-MOSFET having the above advantages into practice. The mobility of the strained Si layer
3
(or strained SiGe layer) can be further enhanced by forming the strained Si layer
3
on the lattice relaxed Si
1−x
Ge
x
buffer layer
4
which satisfies the above condition by epitaxial growth.
The inventor of this application and others have found a method for forming the lattice relaxed Si
1−x
Ge
x
buffer layer on the insulation layer
5
,
4
which includes growth of an Si
1−x
Ge
x
layer (x=0.1) having a low Ge composition ratio and successive thermal oxidation of the Si
1−x
Ge
x
layer (x=0.1) at high temperatures. The method has the following property. As the thermal oxidation process proceeds, Ge in the Si
1−x
Ge
x
layer (x=0.1) is enriched to form an Si
1−x
Ge
x
layer (x>0.5) having a higher Ge composition ratio. At the same time, the Si
1−x
Ge
x
layer (x>0.5) is lattice-relaxed and made thin (see T. Tezuka, N. Sugiyama, T. Mizuno, H. Suzuki and S. Takagi, Extended Abstracts of the 20001 International Conference on Solid State Devices and Materials (Sendai, 2000) p. 472, the entire contents of which are incorporated herein by reference).
The method for forming the lattice relaxed SiGe layer will be explained with reference to
FIGS. 2A
to
2
E.
First, as shown in
FIG. 2A
, an Si
1−x
Ge
x
layer (x=0.1)
11
having a low Ge composition ratio is formed by epitaxial growth on an Si substrate
6
. Then, an insulation layer
5
is formed between the Si substrate
6
and the Si
1−x
Ge
x
layer (x=0.1)
11
by use of an SIMOX method.
Next, a dry oxidation process is performed at a high temperature of 1200° C. Then, as shown in
FIG. 2B
, Ge is removed from an Si oxide layer
12
which is formed on the surface of the structure and Ge is accumulated into an SiGe layer
18
which lies under the Si oxide layer
12
. Thus, the Si
1−x
Ge
x
layer (x>0.5)
18
having a high Ge composition ratio is formed. By the above heat treatment, the Si
1−x
Ge
x
layer (x>0.5)
18
is lattice-relaxed by a slip on the interface with the underlying insulation layer
5
.
Next, as shown in
FIG. 2C
, the Si oxide layer
12
on the lattice relaxed Si
1−x
Ge
x
layer (x>0.5)
18
is removed by use of an ammonium fluoride solution. Then, a strained Si layer
3
(or strained SiGe layer) is formed by epitaxial growth on the lattice relaxed Si
1−x
Ge
x
layer (x>0.5)
18
.
Subsequently, as shown in
FIG. 2D
, an element is separated by mesa-etching.
Next, as shown in
FIG. 2E
, a gate insulation layer
2
, a gate electrode
1
and source/drain regions
7
are formed according to the process for forming an SOI-MOSFET and thus a strained SOI-MOSFET is formed.
The Si
1−x
Ge
x
layer (x=0.1)
11
having the low Ge composition ratio and formed on the insulation layer
5
is thermally oxidized at high temperatures in the step shown in FIG.
2
B. Therefore, Ge atoms are removed from the SiGe oxide layer
11
formed on the surface of the structure and accumulated in the underlying SiGe layer
18
. The insulation layer
5
which lies under the SiGe layer
18
prevents Ge atoms from diffusing into the Si substrate
6
. As a result, the Ge composition ratio of the SiGe layer
18
is increased as the oxidation process proceeds.
Since the lattice constant of SiGe increases as the Ge composition ratio becomes higher, shearing stress occurs on the interface between the insulation layer
5
and the SiGe layer
18
. If a sufficient amount of slip on the interface or plastic deformation of the insulation layer
5
occurs, the SiGe layer can freely expand and contract due to the shearing stress so that lattice relaxation proceeds without dislocation generation.
However, particularly, when the insulation layer
5
is formed of SiO
2
, plastic deformation or slip between the SiGe layer
18
and the insulation layer
5
will not sufficiently occur even if the heat treatment is performed at a temperature which i

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