Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-12-16
2001-04-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C326S016000, C326S039000, C713S500000, C324S076390, C324S076410, C324S076530, C714S022000
Reexamination Certificate
active
06216254
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
The present invention relates the field of integrated circuits, and more particularly, to the design of integrated circuits.
B. Description of Related Art
Computer-based tools have simplified the design and manufacturing processes in the development of integrated circuits. Such tools have made the large scale development and manufacture of application specific integrated circuits (ASIC) possible. An ASIC is an integrated circuit, or “chip,” that has been built for a specific application. Most integrated circuits have general functions, such as combinational logic, shift registers, etc., and are connected to one another on circuit boards. ASICS include such general function circuits that are connected to perform specific applications as systems, such as, a disk controller, a communications protocol, a bus interface, a voice coder, etc. ASICS may include on a single integrated circuit the circuitry that is typically built on a circuit board.
Computer-based tools that ease the process of placing components and routing connections between the components in meaningful integrated circuit layouts may significantly shorten the process of designing ASICS. The use of library of cells, or computer representations or models, of general-purpose circuits and a user interface that has access to the cells in computer-based tools has simplified the routing of connections between ASICS.
The cells may include information about the circuit represented by the cell. The information may be used to verify the correctness of the layout and other aspects of the circuit design. The cells may include information about the inputs, the outputs, the functions of the circuit and any design rules that the tool may use to verify the layout during the design process. The cells may represent circuits having many functions such that entire systems may be designed and manufactured on a semiconductor chip.
One advantage of using computer-based tools to design integrated circuits is that many have simulation capabilities. Integrated circuits may be tested using simulation tools that operate while the integrated circuit is still in layout form, before any prototypes are built.
In addition, computer-based tools make the manufacturing process easier by standardizing the output that is used to specify integrated circuit wafers. Designs may be downloaded to a standard file format and sent to silicon foundries that support that format for manufacture. The testing process may also be made easier by computer-based tools. Automatic test equipment of all types exist to test systems designed on an ASIC or any general integrated circuit.
One problem with computer-based tools is that much of the reliability of the system depends upon the designer and the features of the tools. Guidelines exist to ensure that the ASICS designed are testable and manufacturable. However, there is no way to ascertain that such guidelines are followed.
For example, many ASICS use frequency synthesizers to provide synchronization of events through the generation of one or more frequencies. The frequencies that are being used in ASICS may now exceed 400 MHz. This is a problem because many of the automatic test equipment are not capable of testing systems at higher than 50 MHz. Such test equipment is expensive and difficult to keep current with the technology, which makes manufacturers reluctant to replace test equipment that already works.
ASICS that use frequency synthesizers are typically tested in a couple of ways. First, the circuitry not including the frequency synthesizer is tested in a bypass mode. In the bypass mode, the frequency synthesizer is bypassed and the tester clock is connected to the circuitry excluding the frequency synthesizer. Test patterns generated in this manner may verify the operability of the circuitry.
The circuitry is then tested with frequency synthesizer by using the frequency synthesizer to drive the remaining circuitry to generate test patterns from certain integrated circuit pins to verify the operation of the frequency synthesizer. For this test to work properly, however, the frequency synthesizer must output a phase-locked frequency, that is, the frequency output must be stable. Typically, a phase-lock detect signal is made available to the tester as feedback for when the valid generation of test patterns may begin. Designers may not always make such a signal available. In addition, other guidelines for ensuring the testability of integrated circuits may not have been followed.
It would be desirable to ensure the testability of an integrated circuit automatically, without requiring the designer to follow addition steps or guidelines.
SUMMARY OF THE INVENTION
In view of the above, an improved system for designing integrated circuits is provided. The integrated circuit includes a frequency synthesizer, a master reset input and a function circuit. The frequency synthesizer includes a plurality of frequency outputs for outputting a plurality of output frequency signals generated from a reference frequency at a reference frequency input. The frequency synthesizer generates a lock signal to indicate that one of the output frequency signals is synchronous to the reference frequency. The master reset input is coupled to a reset signal source for receiving a master reset signal to initialize the integrated circuit. The function circuit includes a function reset input for receiving a function reset signal, and a plurality of frequency inputs for receiving at least one of the plurality of output frequency signals from the frequency synthesizer.
The system further includes a testability circuit having a test mode for testing the integrated circuit. In the testability circuit, a reset input is included for receiving the master reset signal. In addition, a reset controller is included for coupling a reset out signal to the function reset input when in the test mode, when the frequency synthesizer generates the lock signal and when the master reset signal is received.
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Gearhardt Kevin J.
Kuppinger Jonathan P.
Pesce Michael S.
LSI Logic Corporation
Smith Matthew
Speight Jibreel
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