Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing
Reexamination Certificate
2010-03-04
2011-12-06
Levin, Naum (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
C716S108000, C716S113000
Reexamination Certificate
active
08074190
ABSTRACT:
A circuit design system, methodology, and software are disclosed for generating circuit capable of consuming less dynamic power. In particular, the circuit design methodology entails modifying an initial circuit design including a clock network coupled to a plurality of edge-triggered flip-flops to generate a modified circuit design that uses pulsed latches driven by pulse generators in place of at least some of the flip-flops. Since pulsed latches use less dynamic power than edge-triggered flip-flops, the modified circuit may consume less dynamic power. The circuit design methodology may further entail adding delay cells for balancing the clock network to compensate for timing effects caused by the insertion of pulse generators. Additionally, the methodology may further include cloning of forbidden clock paths to make more flip-flops eligible for pulsed latch replacement.
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Shibatani et al; “Pulse-latch approach reduces dynamic power”; EE Times-India; Aug. 2006; eetindia.com.
Shibatani, S; Li, A. Pulse-latch approach reduces dynamic powe. EE Times. Jul. 7, 2006. pp. 1-4.
Chen Ming-Chyuan
Ho KunMing
Li Hung-Chun
Alford William E.
Alford Law Group, Inc.
Cadence Design Systems Inc.
Levin Naum
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