Integrated circuit design support apparatus, integrated...

Details Integrated circuit design support apparatus, integrated... Integrated circuit design support apparatus, integrated...

2008-04-16

2011-12-06

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

Reexamination Certificate

active

08074196

ABSTRACT:
Provided is an integrated circuit design support apparatus capable of estimating the optimal wiring length and wiring congestion at the stage of implementing a logical design of an integrated circuit, thereby preventing the do-over of the logical design or functional design caused by a wiring delay that is discovered at a packaging design stage, and shortening the time required for designing the integrated circuit. The present invention is able to accurately estimate the wiring length between the modules and the wiring congestion in the modules at the stage of implementing the logical design of the integrated circuit, and reflect the logical design result of the integrated circuit in the packaging design of the integrated circuit.

REFERENCES:
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2001/0034595 (2001-10-01), Yamaguchi
patent: 2005/0278672 (2005-12-01), Hosono et al.
patent: 2005/0283750 (2005-12-01), Kosugi et al.
patent: 2006/0265678 (2006-11-01), Okabe et al.
patent: 2008/0104562 (2008-05-01), Ichinose
patent: 2005-352916 (2005-12-01), None
patent: 2006-323643 (2006-11-01), None

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