Integrated circuit design method and system

Details Integrated circuit design method and system Integrated circuit design method and system

2007-06-05

2007-06-05

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10973419

ABSTRACT:
A method of designing an integrated circuit where a clock circuit is preformed and a clock connection is determined in a placement process is disclosed. The method includes calculating clock skew between sequential circuits based on clock skew information correlating placement positions of sequential circuits and clock skew between the placement positions, and performing placement in consideration of the calculated clock skew.

REFERENCES:
patent: 6928631 (2005-08-01), Matsumoto
patent: 6941540 (2005-09-01), Kumagai
patent: 2003/0014724 (2003-01-01), Kojima et al.
patent: 2004/0111689 (2004-06-01), Kanaoka et al.

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