Integrated circuit design incorporating a power mesh

Details Integrated circuit design incorporating a power mesh Integrated circuit design incorporating a power mesh

1998-06-29

2002-11-12

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C257S211000, C716S030000, C716S030000

Reexamination Certificate

active

06480989

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns integrated circuits (ICs) and IC design, and particularly relates to the use of a power mesh in an integrated circuit.
2. Description of the Related Art
FIG. 1
provides a simplified cross-sectional view of an integrated circuit chip (or die)
10
, which includes a semiconductor layer
5
, three metal layers
1
to
3
, electrically insulating layers
7
, and passivation layer
8
. Semiconductor layer
5
, which is typically polysilicon, is used for forming the transistors and other electronic devices and may also be used for routing some of the electrical connections between these devices. However, wire routing occupies space on the semiconductor layer
5
which otherwise could be used for the electronic devices. As a result, ordinarily only the shorter electrical connections are formed on semiconductor layer
5
. For the remainder of the connections, metal layers
1
to
3
are provided.
Metal layers
1
to
3
may be formed from any of a variety of materials including aluminum, copper or an electrically conductive alloy. Typically, two to four metal layers are formed on top of semiconductor layer
5
. To simplify the routing process, routing typically is performed using mainly horizontal and vertical trace (or wire) segments. Moreover, to permit such routing to be performed in an orderly manner, each metal layer typically is designated as either a horizontal metal layer or a vertical metal layer. Horizontal metal layers are used primarily for horizontal wire segments and vertical metal layers are used primarily for vertical wire segments. By routing wires in the metal layers
1
to
3
, electrical connections can be made without using valuable space on semiconductor layer
5
. Between metal layers
1
and
2
, between metal layers
2
and
3
, and between metal layer
1
and semiconductor layer
5
is an electrically insulating layer
7
, which typically is formed as an oxide film. Connections between any of metal layers
1
to
3
and semiconductor layer
5
are made using interlayer holes called vias. Passivation layer
8
functions to prevent the deterioration of the electrical properties of the die caused by water, ions and other external contaminants, and typically is made of a scratch-resistant material such as silicon nitride and/or silicon dioxide.
FIG. 2
provides a representational illustration of the layout of integrated circuit die
10
. The logic circuitry of integrated circuit
10
is formed on the interior portion
20
of the semiconductor layer
5
. The logic portion
20
includes a number of functional circuit blocks that can have different sizes and shapes. The larger blocks can include, for example, central processing units such as CPU
21
, read-only memories such as ROM
22
, clock/timing units such as clock/timing unit
23
, random access memories such as RAMs
24
, and input/output (I/O) units such as I/O unit
25
for providing an interface between CPU
21
and peripheral devices. These blocks, commonly known as megacells, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries. The logic portion
20
further includes tens of thousands, hundreds of thousands or even millions of additional small cells
26
. Each cell
26
represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries. As used herein, the term “cells” refers generically to megacells, such as elements
21
to
25
, as well as small cells
26
. It is also noted that the “logic portion”
20
does not necessarily consist solely of logic processing circuitry, but may include circuits such as phase-locked loops containing both digital and analog portions, as well as circuits which perform purely analog processing.
Along the periphery of the semiconductor layer
5
are I/O buffer cells
16
. Each of the I/O buffer cells
16
is either a power signal buffer, a ground signal buffer or an information signal buffer. As used herein, the term “information signal” is defined to mean a signal that conveys any type of information and includes, for example, clock, data, address and control signals. In a wire-bond IC chip, each such buffer cell
16
generally has connected to it at least one metal bonding pad
18
which is used as an electrical connection for an I/O signal. Thus, bonding pads
18
provide the electrical connections between the die and the package containing the die. Typically, pins on the package then connect the IC to other electronic components on a printed circuit board.
Certain of pads
18
are connected to external power and ground. Each such pad is connected to a buffer cell
16
, which in turn is connected to one of the chip's power or ground rings, as the case may be. More specifically, power ring
32
and ground ring
33
supply power (VDD) and ground (VSS) to the buffer cells
16
. Similarly, power ring
30
and ground ring
31
provide power (VDD2) and ground (VSS2) to the internal logic circuitry
20
. In order to isolate the internal logic power and ground from the I/O buffer power and ground, ordinarily certain pad/buffer pairs are connected only to the internal logic power/ground rings
32
and
33
, and different pad/buffer pairs are connected only to the buffer power/ground rings. Power and ground rings
30
to
33
ordinarily are implemented on the metal layers, such as metal layers
1
and
2
.
FIG. 3
illustrates one conventional technique for routing power and ground from rings
30
and
31
, respectively, to electronic components in the interior logic portion
20
of the IC die
10
. In
FIG. 3
, cells are arranged in cell columns
41
to
44
. Each cell generally has a standard width but can have different lengths. Examples of such standard-width cells include cells
51
to
53
. To supply power and ground to the cells in this configuration, parallel vertical power rails
61
and ground rails
62
are used. Specifically, each cell column is provided with a power rail
61
and a ground rail
62
. Typically, power rails
61
and ground rails
62
are implemented on a vertical metal layer, such as metal layer
1
. Power rails
61
and ground rails
62
then connect to the standard-width cells using vias from metal layer
1
to semiconductor layer
5
at the required connection points. As shown in
FIG. 3
, power rails
61
run the entire length of interior logic portion
20
from the top side of power ring
30
to the bottom side of power ring
30
. Similarly, ground rails
62
run the entire length of interior logic portion
20
from the top side to the bottom side of ground ring
31
. Also as shown in
FIG. 3
, the foregoing configuration may also include cells having non-standard widths, such as cell
55
. In this case, external power ring
57
and external ground ring
58
supply power and ground to cell
55
and also serve to jog the power rails
61
and ground rails
62
around the non-standard cell
55
.
In the foregoing conventional arrangement, the power rails
61
and ground rails
62
typically are designed to be wide enough to carry the amount of current required by their respective cell columns. However, in addition to insuring adequate current-carrying capacity, another concern is voltage drop. For example, while the voltage at the power/ground ring might be approximately 2.5 V, voltage typically drops closer toward the center of the die and may be insufficient to adequately power the cells near the center. However, because a pair of power/ground rails must be provided for each cell column, simply widening the rails enough to prevent excessive voltage drop often may be impractical.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing problems by providing an integrated circuit which uses a power mesh.
According to one aspect, the invention is an integrated circui

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