Integrated circuit design for signal integrity, avoiding...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

07089513

ABSTRACT:
A method, system and program product for designing an integrated circuit (IC) for signal integrity. The invention conducts a signal integrity analysis on an IC design; identifies any field effect transistor (FET) that causes a signal integrity failure in the case that the IC design fails the signal integrity analysis; and modifies an edge of a failing FET that is closer than a threshold distance to a well edge. The invention eliminates the manual, iterative procedure for determining the device causing a signal integrity failure due to well proximity effects.

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Polishchuk et al., “CMOS Vt-Control Improvement Through Implant Lateral Scatter Elimination”, Sep. 2005, IEEE International Symposium on Semiconductor Manufacturing, Paper Digest, pp. 193-196.
“BSIM4.5.0. Manual: Chapter 14: Well Proximity Effect Model”, 2005, University of California-Berkeley, 14-1-14-7.

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