Integrated circuit design flow with capacitive margin

Details Integrated circuit design flow with capacitive margin Integrated circuit design flow with capacitive margin

2002-07-10

2004-10-26

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S013000

Reexamination Certificate

active

06810505

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods of designing electronic circuits. More specifically, but without limitation thereto, the present invention relates to a method of designing integrated circuits that simplifies the design flow of integrated circuits by introducing appropriate capacitive margins.
BACKGROUND OF THE INVENTION
In previous methods for designing integrated circuits, several iterations of cell placement, routing and signal analysis of the capacitive effects of the interconnections are typically required to satisfy timing constraints, sometimes requiring weeks of cross-talk analysis after parasitic extraction is performed on the circuit floorplan. Because cross-talk analysis is so time consuming, it presents a significant bottleneck in the design cycle of integrated circuits.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a design flow for an integrated circuit design includes a capacitive margin that significantly reduces the number of iterations in the design flow and avoids the necessity of cross-talk analysis. Instead, an incremental crosstalk delay is estimated and associated with each net. Each critical path has a corresponding individual incremental crosstalk delay that is added to the path delay. The incremental crosstalk delay accounts for real interconnect capacitance and coupling effects for each interconnect by scaling the interconnect and coupling capacitances with individually adjustable margin multipliers.


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