Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-10
2003-02-04
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06516459
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated device design. More particularly, the invention relates to verification and correction techniques that can be used in an integrated device design and manufacturing process.
BACKGROUND OF THE INVENTION
As integrated circuits (ICs) become more dense, the widths of lines and components, as well as the separation between lines becomes increasingly smaller. Currently, deep sub-micron (<0.25 &mgr;m) processes are being used. However, with deep sub-micron processes, silicon yield is affected by several factors including reticle/mask pattern fidelity, optical proximity effects, and diffusion and loading effects during resist and etch processing. Typical problems include line-width variations that depend on local pattern density and topology and line end pullback.
Optical and process correction (OPC) can be used to improve image fidelity. Optical proximity correction is a subset of optical and process correction. OPC techniques include, for example, introduction of additional structures to the IC layout that compensate for various process distortions and layout modification to compensate for optical distortions. Two general categories of OPC are currently in use: rule-based OPC and model-based OPC. In rule-based OPC, a reticle layout is modified according to a set of fixed rules for geometric manipulation. However, rule-based OPC has limited capability and when more complex OPC is desired, model-based OPC is used.
In model-based OPC, an IC structure to be formed is modeled and a threshold that represents the boundary of the structure on the wafer can be determined from simulated results generated based on the model used. Simple forms of model-based OPC generate a simulated aerial image having a threshold to predict the structure to be manufactured.
Current OPC techniques generally work well for binary (i.e., single exposure, non-phase shifted) masks. However, for manufacturing processes where two or more masks are used to manufacture a single IC layer, current OPC techniques may not converge to an acceptable result. What is needed is improved OPC that can be used with multiple exposure manufacturing techniques.
SUMMARY OF THE INVENTION
A simulated layer of an integrated device to be manufactured is compared to a target layout representing a desired integrated device layer. The simulation is based on layouts of multiple reticles corresponding to the layer of the integrated device. An edge placement error is determined for one or more layout fragments based, at least in part, on the comparison of the simulated integrated device layer and the target layout. In one embodiment, one or more fragments of the layouts of the multiple reticles are mapped to corresponding fragments of the target layout. Each fragment of the layouts of the multiple reticles are mapped to one fragment of the target layout. One or more fragments of the multiple reticle layouts are modified based, at least in part, on an edge placement error of the fragment of the target layout to which the respective reticle fragments are mapped.
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patent: WO 01/65315 (2001-09-01), None
Blakely , Sokoloff, Taylor & Zafman LLP
Garbowski Leigh M.
Mentor Graphics Corporation
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