Integrated circuit design based on scan design technology

Details Integrated circuit design based on scan design technology Integrated circuit design based on scan design technology

2011-04-05

2011-04-05

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S093000, C326S008000, C714S726000

Reexamination Certificate

active

07919981

ABSTRACT:
An integrated circuit is provided with a scan chain including a scan flip-flop and a dummy block. The dummy block has a clock terminal receiving a clock signal, a scan input terminal connected to a scan data line within the scan chain, and a scan output terminal connected to another scan data line within the scan chain. The dummy block is configured to output data on the scan output terminal in response to input data fed to the scan input terminal, not responsively to the clock signal.

REFERENCES:
patent: 7383523 (2008-06-01), Inoue
patent: 2006/0066357 (2006-03-01), Inoue
patent: 2006/0075315 (2006-04-01), Cruz et al.
patent: 2008/0092002 (2008-04-01), Shimooka
patent: 2005-322694 (2005-11-01), None
patent: 2006-128635 (2006-05-01), None

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