Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-03-13
2007-03-13
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
10103895
ABSTRACT:
An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.
REFERENCES:
patent: 5218551 (1993-06-01), Agrawal et al.
patent: 5333032 (1994-07-01), Matsumoto et al.
patent: 5475608 (1995-12-01), Masuoka
patent: 5663889 (1997-09-01), Wakita
patent: 5787268 (1998-07-01), Sugiyama et al.
patent: 5815655 (1998-09-01), Koshiyama
patent: 6086625 (2000-07-01), Shouen
patent: 6117183 (2000-09-01), Teranishi et al.
patent: 6167561 (2000-12-01), Chen et al.
patent: 6169968 (2001-01-01), Kabuo
patent: 6240541 (2001-05-01), Yasuda et al.
patent: 6249902 (2001-06-01), Igusa et al.
patent: 6308305 (2001-10-01), Sugiyama et al.
patent: 6567965 (2003-05-01), Sakagami et al.
patent: 6665852 (2003-12-01), Xing et al.
patent: 6748574 (2004-06-01), Sasagawa et al.
Schulz et al., “Hierarchical physical design system”, ompEuro '89., ‘VLSI and Computer Peripherals. VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks’, Proceedings. , 8-12, May 1989, pp. 5/20-5/24.
Kim et al., “An improved hierarchical placement technique using clustering and region refinement”, Circuits and Systems, 1996., IEEE Asia Pacific Conference on , Nov. 18-21, 1996, pp. 393-396.
Amano Yasuo
Ishikawa Yoichiro
Makino Yukio
Nakanishi Yoshiko
Seki Hiroshi
Chiang Jack
Fujitsu Limited
Rossoshek Helen
Staas & Halsey , LLP
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