Integrated circuit delay lines having programmable and phase...

Details Integrated circuit delay lines having programmable and phase... Integrated circuit delay lines having programmable and phase...

1998-11-20

2001-05-15

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S161000, C327S270000, C375S375000, C365S189070

Reexamination Certificate

active

06232812

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 97-62042, filed Nov. 21, 1997, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuits having delay lines therein.
BACKGROUND OF THE INVENTION
In a synchronous DRAM device, the time delay for generating output data in response to a read command received in synchronization with a clock is generally equal to a CAS latency (CL) times a clock period (tCK) plus an access time (tAC). Here, the CAS latency is generally an integer multiple or a half integer multiple of the clock period tCK. However, as the scale of integrated circuits and systems become larger, the delay time associated with the output of data in a synchronous DRAM must be carefully and variably controlled. In particular, in a system containing a DRAM controller and a plurality of synchronous DRAM devices electrically coupled thereto, it would preferable if the delay time associated with the output of data from each DRAM device could be independently controlled to inhibit the likelihood of simultaneous arrival of large quantities of data at the DRAM controller.
To provide independent control of the delay time, integrated circuit delay lines have been proposed. In an integrated circuit delay line which can be programmed, coarse programmable delay and fine programmable delay can typically be separately controlled. The coarse programmable delay is typically an integer or one-half integer multiple of the period T of an input clock CLK, and the fine programmable delay is less than an integer or one-half integer multiple of the period T. An exemplary delay line is disclosed in an article by Y. Okajima et al. entitled “Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface”, IEICE Trans. Electron., Vol. E79-C, No. 6, pp. 798-807, June (1996). Unfortunately, the timing of the coarse and fine delays may be influenced by changes in operating voltage, temperature and process variations. Thus, there continues to be a need for integrated circuit delay lines having improved characteristics.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit delay lines.
It is a further object of the present invention to provide programmable integrated circuit delay lines.
It is still a further object of the present invention to provide programmable integrated circuit delay lines which can match the full or half-period of an input clock, even if operating voltages, temperature or process variations influence the timing of the input clock.
These and other objects, advantages and features of the present invention are provided by programmable delay lines which include a delay circuit having an input and a plurality of outputs (D
1
-Dn) which each provide a respective delayed version of a periodic input signal provided to the input. A delay switch is also provided to pass one of the plurality of outputs of the delay circuit to a switch output, in response to a digital control signal (P
1
-Pn). A preferred phase comparing circuit is also provided. This phase comparing circuit compares the input signal against the delayed versions of the input signal (at the plurality of outputs D
1
-Dn) and generates a digital phase signal (F
1
-Fn) that identifies which of the delayed versions of the input signal is in-phase with the input signal. The programmable delay line also includes a pointer which generates the digital control signal in response to the digital phase signal and a plurality of pointer control signals (S
0
, S
1
and WS).
According to a preferred embodiment of the present invention, the programmable delay line further includes a first comparator which generates a first equivalence signal (QWD) in a first logic state (e.g., logic 1) if the digital phase signal (F
1
-Fn) is equivalent to the digital control signal (P
1
-Pn). A second comparator is also provided which generates a second equivalence signal (QWU) if the digital control signal indicates an initialized state of the pointer (e.g., when P
1
=1). A command decoder is also provided which generates the plurality of pointer control signals in response to up and down command signals (UP, DOWN) and the first and second equivalence signals (QWD, QWU). According to a preferred aspect of the present invention, the plurality of pointer control signals (S
0
, S
1
, WS) cause the pointer to become initialized (P
1
-Pn=10 . . . 00) if the up command signal (UP) is applied to the command decoder while the first equivalence signal (QWD) is in the first logic state. The plurality of pointer control signals also preferably cause the pointer to become initialized (e.g., reset) if the up and down command signals are simultaneously applied to the command decoder. Alternatively, the plurality of pointer control signals will cause the pointer to be loaded with the digital phase signal (F
1
-Fn) if the down command signal (DOWN) is applied to the command decoder while the second equivalence signal (QWU) is in the first logic state.
According to other preferred aspects of the present invention, the delay circuit comprises a plurality of serially connected delay units, the phase comparing circuit comprises a plurality of phase comparators and each phase comparator comprises a latch having a data input which can be electrically connected to a respective one of the outputs of the delay circuit. Each phase comparator may also comprises a pair of transmission gates, with one transmission gate turning-on when the periodic input signal transitions from 0→1 and the other transmission gate turning-on when the periodic input signal transitions from 1→0. The pointer may also comprise a plurality of multiplexers configured so that an input of each of the plurality of multiplexers receives a respective bit of the digital phase signal (F
1
-Fn) when a pointer control signal (e.g., WS) is in a first logic state and receives a logic 1 or logic 0 reference signal when the first pointer control signal is in a second logic state, opposite the first logic state. The pointer may also comprise a plurality of latches configured so that each of the plurality of latches has a data input electrically coupled to an output of a respective multiplexer and a clock input electrically coupled to the input of the delay circuit.


REFERENCES:
patent: 4755704 (1988-07-01), Flora et al.
patent: 4868514 (1989-09-01), Azevedo et al.
patent: 5049766 (1991-09-01), Van Driest et al.
patent: 5451894 (1995-09-01), Guo
patent: 5901190 (1999-05-01), Lee
Okajima et al., “Digital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface”, IEEE Trans. Electron., vol. E79-Cc, No. 6, Jun. 1996, pp. 798-807.

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