Integrated circuit defect tolerant architecture

Details Integrated circuit defect tolerant architecture Integrated circuit defect tolerant architecture

1995-08-23

1997-07-08

Tran, Minh-Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

257246, 257249, 257250, H01L 27148

Patent

active

056464274

ABSTRACT:
A structure for a charge coupled device (CCD) to minimize effects of masking defects of a predetermined dimensional extent includes a plurality of sets of conductors, a plurality of strapping networks and a connection matrix of via contacts. Each set of the plurality of sets of conductors includes a plurality of parallel elongate first conductors oriented in a first direction and disposed substantially in a first plane, each first conductor being comprised of a first material and characterized by a first sheet resistance per square of conductor. Each network of the plurality of strapping networks includes a plurality of parallel elongate second conductors oriented in a second direction transverse to the first direction and being disposed substantially in a second plane insulatively spaced apart from the first plane, each second conductor being comprised of a second material and characterized by a second sheet resistance per square of conductor, the second sheet resistance being less than the first sheet resistance. Each via contact of the connection matrix of via contacts connects a conductor of the plurality of first conductors of one of the sets of conductors with a conductor of the plurality of second conductors of one of the strapping networks, the connection matrix having a first via contact. Distances between the first via contact and each other via contact of the connection matrix are greater than the predetermined dimensional extent while a first lateral spacing between adjacent conductors of the plurality of first conductors is less than the predetermined dimensional extent, and while a second lateral spacing between adjacent conductors of the plurality of second conductors is less than the predetermined dimensional extent.

REFERENCES:
patent: 4163239 (1979-07-01), Carter
patent: 4262297 (1981-04-01), Partridge
patent: 4375652 (1983-03-01), White
patent: 4870293 (1989-09-01), Elabd
patent: 5073808 (1991-12-01), Kinoshita
patent: 5194751 (1993-03-01), Yonemoto et al.
patent: 5212503 (1993-05-01), Saito et al.
patent: 5332917 (1994-07-01), Lee et al.
S.M. Sze, "VLSI Technology", McGraw-Hill, New York, 1983, pp. 604-613, Chap. 14, Yield and Reliability written by W.J. Bertram.
Randall L. Geiger et al., "VLSI Design Techniques for Analog and Digital Circuits", McGraw-Hill, New York, 1990, pp. 19-29.

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