Integrated circuit cooling device

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents

Reexamination Certificate

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Details

C257S093000, C257S467000, C257S470000, C257S930000

Reexamination Certificate

active

06800933

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to an integrated circuit incorporating Peltier heat transfer devices and to methods of making the same.
2. Description of the Related Art
Heat management plays a vital role in the process of designing most electrical devices. However, the microscopic geometries and tight electrical performance windows of integrated circuits present special challenges. Elevated chip operating temperatures impose constraints on the performance of the circuit in several ways. Chip operating temperature has a direct impact on the maximum available clocking speed and thus the overall speed performance of the integrated circuit. Furthermore, higher operating temperatures restrict the permissible operating voltage and ambient temperature environment of the chip. Lastly, chip life span is adversely impacted by higher operating temperatures. If the available mechanisms for integrated circuit heat dissipation cannot adequately handle the I
2
R heat propagation, compromises in the speed performance, the operating voltage, the applications and the design life span of the integrated circuit may have to be made.
In many conventional integrated circuit designs heat sinks with or without forced convection are used to provide macro scale cooling. A conductive heat transfer pathway is provided between the die and a heat sink that is coupled to the integrated circuit or to a package holding the integrated circuit. Many such conventional heat sinks consist of a plurality of metallic heat fins. The conduction heat flow from the die to the die package is limited by the thermal resistance of the heat flow pathway between the die and the package. The thermal resistance is a function of the thermal conductivities of the die and the package and the contact area between the two structures.
In some cases, there may be localized areas of high temperature or “hot spots” within an integrated circuit. If the semiconductor substrate on which the integrated circuit is formed has a relatively high coefficient of thermal conductivity, then conductive heat transfer from the hot spot into the bulk substrate may provide adequate temperature control, particularly if convection package cooling is applied. However, if the conductive heat transfer pathway away from the hot spot presents a high thermal resistance, then more localized thermal management may be indicated.
Silicon-on-insulator (“SOI”) substrates represent examples of such high thermal resistance structures. In SOI substrates, junction isolation is provided by surrounding active device regions with an insulator. A typical SOI substrate includes a plurality of silicon islands formed on an insulating layer, usually of oxide. The silicon islands are also isolated laterally by an insulator, again usually an oxide. Thus, thermal conduction from the device regions must proceed through the surrounding oxide. Since oxide has a coefficient of thermal conductivity that is as much as factor of one hundred smaller than silicon, the thermal resistance for a silicon-to-oxide pathway is much larger than a similar pathway through silicon alone.
Integrated circuit fabrication on SOI substrates holds the promise of significant device scaling through increased packing density. However, without adequate localized heat management of such substrates, significant design hurdles may remain.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a circuit device is provided that includes an insulating substrate, a semiconductor structure positioned on the insulating substrate and a Peltier effect heat transfer device coupled to the insulating substrate to transfer heat between the semiconductor structure and the insulating substrate.
In accordance with another aspect of the present invention, a circuit device is provided that includes a semiconductor substrate, an insulating substrate positioned on the semiconductor substrate and a semiconductor island positioned on the insulating substrate. A Peltier effect heat transfer device is positioned in the insulating substrate proximate the semiconductor island to transfer heat between the semiconductor island and the insulating substrate.
In accordance with another aspect of the present invention, an integrated circuit is provided that includes an insulating substrate and a semiconductor layer positioned on the insulating substrate. The semiconductor layer has a plurality of active semiconductor island regions. A plurality of circuit devices is positioned on the semiconductor layer. At least one Peltier effect heat transfer device is coupled to the insulating substrate to transfer heat between at least one of the active semiconductor island regions and the insulating substrate.
In accordance with another aspect of the present invention, a method of fabricating a circuit structure is provided that includes forming an insulating substrate, forming a Peltier effect heat transfer device in the insulating substrate and forming a semiconductor film on the insulating substrate proximate the Peltier effect heat transfer device.


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Victor Rudometov et al.;Peltier coolers(http://www.digit-life.com/articles/peltiercoolers/); pp. 1-9; 2000.
Tillman Steinbrecher;The Heatsink Guide:Peltier coolers(http://www.heatsink-guide.com/peltier.htm); pp. 1-5; Mar. 23, 2001.
Mr. Sengebusch;Mirco peltier elements(http://www.peltierelement.com/english/peltierelement/micro.html); pp. 1-3; Jul. 12, 2000.

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