Integrated-circuit configuration having fast local access time

Details Integrated-circuit configuration having fast local access time Integrated-circuit configuration having fast local access time

1989-11-29

1991-04-23

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Including signal comparison

36518905, G11C 1140

Patent

active

050105221

ABSTRACT:
An integrated-circuit memory-array configuration for providing less total access time when used in conjunction with a microprocessor. The configuration includes a line buffer with perhaps 256 latches for storing data, and first and second pipeline circuits for sensing linearity and locality of access information pertaining to the requested data. When used with a microprocessor that is programmed with repeated requests for the same data, a majority of the data requests will be transmitted quickly from the line buffer. If the data requests are not in the line buffer, the configuration furnishes a signal to the microprocessor and the requested data are moved from the floating-gate memory cell array to the line buffer for subsequent transmittal to the microprocessor.

REFERENCES:
patent: 3771145 (1973-11-01), Wiener
patent: 4330852 (1982-05-01), Redwine et al.
patent: 4739497 (1988-04-01), Itoh et al.
patent: 4817058 (1989-03-01), Pinkham
"TMS27C212 1,048,576-Bit BurstMode.TM. UV Erasable Programmable Read-Only Memory TMS27C212 1,048,576-Bit BurstMode.TM. Programmable Read-Only Memory", Texas Instruments Product Review 5/89, pp. 1-16.
Ashmore et al., "Session 2: High-Speed SRAMs WAM 2.8: A 20ns 1 Mb CMOS BurstMode EPROM", 1989 IEEE International Solid-State Circuits Conference, pp. 40-41.

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