Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-20
2003-07-15
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S307000, C257S308000, C257S309000
Reexamination Certificate
active
06593614
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated circuit configuration having at least one transistor and one capacitor, and also to a method for fabricating it.
With regard to ever faster components at a higher integration level, the feature sizes of integrated circuit configurations decrease from generation to generation. At the present time, the integrated circuit configurations are usually realized using a planar silicon technology in which the components are disposed next to one another and are connected to one another via a plurality of metallization planes.
If an integrated circuit configuration contains a transistor, then its packing density can be increased by configuring the transistor as a vertical transistor. The reference by L. Risch et al., titled “Vertical MOS-Transistors With 70 nm Channel Length”, ISSDERC 1995, pages 101 to 104, describes vertical MOS transistors in which, in order to fabricate them, layer sequences having layers corresponding to source, channel and drain are formed and are annularly surrounded by a gate electrode.
A further possibility for increasing the packing density of an integrated circuit configuration consists in disposing two components one above the other. German Patent DE 195 19 160 C1 proposes a dynamic random access memory (DRAM) cell configuration in which a storage capacitor is disposed above a selection transistor. A first source/drain region, a channel region disposed underneath and a second source/drain region, disposed underneath, of the selection transistor are parts of a projection-like semiconductor structure which is annularly surrounded by a gate electrode. Mutually adjoining gate electrodes form word lines. The first source/drain region also acts as a first capacitor electrode of the storage capacitor. A capacitor dielectric is disposed over the first capacitor electrode, and a second capacitor electrode is disposed over the capacitor dielectric, the second capacitor electrode acting as a common capacitor plate for all the storage capacitors of the DRAM cell configuration. The area of a memory cell of the DRAM cell configuration may be 4F
2
, where F is the minimum feature size that can be fabricated in the technology used.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit configuration having at least one transistor and one capacitor, and a method for fabricating it, that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit. The integrated circuit contains a transistor having a first source/drain region and a second source/drain region, and a capacitor having a dielectric layer, a first capacitor electrode, and a second capacitor electrode adjoining the dielectric layer. An insulating layer is provided and a patterned conductive layer is disposed above the insulating layer. A structure through which the transistor can be driven is disposed beneath the patterned conductive layer, the insulating layer isolating the structure from the patterned conductive layer. A vertical conductive structure having a first region, a second region and a third region disposed one above another with respect to a vertical axis is provided, the second region is disposed between the first region and the third region. The first region of the vertical conductive structure laterally adjoins the conductive layer, and the third region of the vertical conductive structure adjoins the first source/drain region of the transistor. The patterned conductive layer and the vertical conductive structure together form the first capacitor electrode of the capacitor, and the dielectric layer adjoins the vertical conductive structure and the conductive layer. An insulating structure laterally adjoins the structure through which the transistor can be driven. The second region of the vertical conductive structure laterally adjoins the insulating structure.
The invention is based on the problem of specifying an integrated circuit configuration having at least one transistor and one capacitor in which the first source/drain region of the transistor is connected to the first capacitor electrode of the capacitor, in which the capacitor has a high capacitance and which can nevertheless be fabricated with a high packing density.
In the case of an integrated circuit configuration according to the invention, a structure via which the transistor can be driven and the patterned conductive layer which is part of the first capacitor electrode of the capacitor are disposed one above the other. An insulating layer isolates the structure via which the transistor can be driven from the conductive layer. Disposing the conductive layer and the structure via which the transistor can be driven one above the other increases the packing density of the circuit configuration compared with embodiments of the prior art, in which the first capacitor electrode and the structure via which the transistor can be driven are disposed next to one another.
A vertical conductive structure is provided as a further part of the first capacitor electrode. Which structure, having a first region, laterally overlaps the conductive layer, is insulated, at a second region, by an insulating structure from the structure via which the transistor can be driven, and, with a third region, overlaps a first source/drain region of the transistor. The second region is disposed between the first region and the third region. The first region, the second region, and the third region of the vertical conductive structure are disposed one above the other with respect to a vertical axis, that is to say an axis that is vertical with respect to the layer planes. The insulating structure laterally adjoins the structure via which the transistor can be driven. The second region of the vertical conductive structure laterally adjoins the insulating structure. A capacitor dielectric adjoins the conductive layer and the vertical conductive structure, and is in turn adjoined by a second capacitor electrode of the capacitor. On account of the vertical conductive structure, an effective surface area of the first capacitor electrode is greater than its projection onto a horizontal plane, which is highly advantageous since a capacitance of the capacitor can be increased without reducing the packing density of the circuit configuration.
Furthermore, a particularly high packing density of the circuit configuration results from the fact that at least one sidewall of the structure via which the transistor can be driven is utilized for enlarging the surface area of the first capacitor electrode.
Moreover, it is advantageous that the vertical conductive structure allows the connection between the first source/drain region of the transistor and the conductive layer even though, in terms of the height, that is to say with respect to the vertical axis, the structure via which the transistor can be driven is disposed between them.
A “spacer” is understood to be a structure formed on a lateral area of an at least approximately step-shaped structure when material is deposited essentially conformally and etched back anisotropically until horizontal areas of the step-shaped structure are uncovered.
It is advantageous to configure the vertical conductive structure as a spacer since the spacer has a small horizontal dimension, and a particularly high packing density can thus be attained. The connection between the first source/drain region of the transistor and the conductive layer occupies a particularly small horizontal area, which is why a horizontal cross section of the capacitor or of the first source/drain region may also turn out to be small.
The transistor may be disposed higher than the conductive layer. In this case, the third region of the vertical conductive structure is disposed higher than the first region of the vertical conductive structure.
The transistor may be disposed at a
Hofmann Franz
Krautschneider Wolfgang
Infineon-Technologies AG
Loke Steven
Maybeck Gregory L.
Tran Thien F
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