Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-21
2002-08-27
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S309000, C438S253000, C438S396000
Reexamination Certificate
active
06441424
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated circuit configuration having at least one capacitor and a method for producing an integrated circuit configuration having at least one capacitor.
In the development of new integrated circuit configurations, one goal is increased packing density. That is usually achieved currently with planar silicon technology.
One possible way of increasing the packing density is to make a capacitor of a circuit configuration not in planar form but rather in a trench (see, for Instance, an article entitled “Trench and Compact structures for DRAMs”, by P. Chatterjee et al, in IEDM 86, pp. 128-131). The trench is created by a photolithographic process in a semiconductor substrate in which the circuit configuration is disposed. In the case of structure sizes below 200 nm, that concept becomes problematic, since when the trench structure is created edge offsets often occur, along which conductive channels form that then extend through neighboring components of the circuit configuration. Problems also arise in producing the trench, because of the extreme differences between the width and depth of the capacitor.
An article entitled “A 1.28 &mgr;m
2
Bit-Line Shielded Memory Cell Technology for 64 Mb DRAMs”, by Y. Kawamoto et al, in Techn. Digest of VLSI Symposium 1990, p. 13, proposes forming a capacitor as a stacked capacitor. Increasing the surface area and thus the capacitance of the storage capacitor requires a relatively complicated structure of polysilicon, which is all the more difficult to make as the packing density becomes higher.
When components are created by photolithographic processes, a limit is set on the packing density, on one hand by the minimal structural size F that can be achieved in the particular technology and on the other hand by inaccuracies in the adjustment, which amount to approximately ⅓ F. In order to further increase the packing density, German Patent DE 195 19 160 C1, for instance, has proposed creating components in a DRAM cell configuration in self-adjusted form, that is without using masks which have to be adjusted.
In an article entitled “Developments in Porous Silicon Research” by V. Lehmann, in Material Letters 28 (1996), pp. 245-249, the creation of capacitors in a silicon substrate is described. To that end, notches are made in the silicon substrate through the use of a photolithographic process, and pores are created from those notches by ensuing electrochemical etching. The pores are then provided with a capacitor dielectric and with storage nodes.
It is known from an article entitled “Fabrication of Three-Dimensional IC Using ‘Cumulatively Bonded IC’ (Cubic) Technology” by Y. Hayashi et al, in Symposium on VLSI Technology (1990), pp. 95-96, to connect substrates that include components through the use of an adhesive layer of polyimide. Contacts between the substrates are made through tungsten pins and associated large-area indentations, which are filled with a gold-indium alloy.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit configuration having at least one capacitor and a method for producing the same, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which the integrated circuit configuration can be made with an especially high packing density.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit configuration having at least one capacitor, comprising a first substrate having a surface and at least one zone adjoining the surface; a second substrate having a surface with a region; at least two capacitor elements disposed in the at least one zone of the first substrate and spaced apart by a given distance; at least one contact disposed in the region of the surface of the second substrate, the at least one contact having a contact surface adjoining at least one of the capacitor elements, the contact surface having a cross section parallel to the surface of the first substrate, and the cross section having at least one dimension larger than the given distance; and the capacitor elements including capacitor elements disposed adjacent the contact surface and forming a capacitor.
With the objects of the invention in view, there is also provided a method for producing an integrated circuit configuration having at least one capacitor, which comprises producing at least two capacitor elements in at least one zone of a first substrate adjoining a surface of the first substrate, and spacing the capacitor elements apart by a given distance; producing at least one contact on a second substrate, in a region of a surface of the second substrate, and setting at least one dimension of a cross section of a contact surface of the at least one contact parallel to the surface of the first substrate to be larger than the given distance; joining the first substrate and the second substrate, with the contact surface adjoining at least one of the capacitor elements; and forming a capacitor of at least one of the capacitor elements adjoining the contact surface.
In the circuit configuration of the invention, the first substrate is connected to the second substrate. The capacitor is disposed in the first substrate, and the contact is disposed in the second substrate. The contact surface of the contact adjoins the capacitor. The contact connects the capacitor with a portion of the circuit configuration that is disposed in the second substrate. The capacitor includes at least one of two capacitor elements, which are disposed in a zone of the first substrate adjoining a surface of the first substrate. A cross section of the contact surface that is parallel to the surface is larger in at least one dimension than a distance between the two capacitor elements.
In accordance with another feature of the invention, the adjustment tolerance when the capacitor is being contacted, that is when the substrates are being connected, can be increased without decreasing the packing density if the contacting first defines which one of the capacitor elements forms the capacitor. To that end, the contact surface in at least one dimension is also larger than a distance between one of the capacitor elements and one edge of the zone. In that case, the contact surface need not be disposed in a particular portion but rather can be disposed in any arbitrary portion of the zone, since in every case the contact surface adjoins at least one of the capacitor elements, which then defines the capacitor. The larger the zone, the greater the adjustment tolerance. Connecting the first substrate to the second substrate can be carried out in an essentially unadjusted manner, if the capacitor elements are distributed over the first substrate in such a way, and a contact surface of the contact is so large, that when the substrates are connected the contact in every case adjoins at least one of the capacitor elements, which then defines the capacitor.
The packing density becomes higher, as the capacitor elements become closer together and as the contact surface becomes smaller. A high adjustment tolerance and a high packing density can accordingly be attained if the zone is large, many capacitor elements are disposed in the zone at short distances from one another, and the dimension of the cross section of the contact surface is only slightly greater than the distances. In that case, distances between the edge of the zone and the capacitor elements neighboring it are preferably no greater than the distance between capacitor elements neighboring one another.
In accordance with a further feature of the invention, the capacitor includes more than one capacitor element. This increases the surface area and thus the capacitance of the capacitor. In that case, the contact surface is correspondingly larger.
In accordance with an added feature of the invention, the adjustment tolerance can be increased in this case as well, if the cont
Hönlein Wolfgang
Klose Helmut
Lehmann Volker
Reisinger Hans
Estrada Michelle
Fourson George
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
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