Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-04
2003-06-10
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S306000, C257S309000, C257S368000, C257S379000
Reexamination Certificate
active
06576948
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an integrated circuit configuration and a method for manufacturing it.
Efforts are generally being made to generate an integrated circuit configuration, i.e. a circuit that is integrated in a substrate, with an ever higher packing density.
German Patent DE 197 27 436 C1 describes a DRAM cell configuration in which a memory cell contains a first transistor, a diode structure and a second transistor. The first transistor and the second transistor share between them a common source/drain region and are connected between a voltage terminal and a bit line. A gate electrode of the second transistor is connected to a word line. The diode structure is connected between a gate electrode of the first transistor and the common source/drain region. The transistors are disposed one over the other and are embodied as vertical MOS transistors. The common source/drain region is disposed in a semiconductor structure at whose edges gate electrodes of the transistors in the form of spacers are disposed. The diode structure is composed of a Schottky diode and a tunnel diode which are connected in series. The tunnel diode is formed by the gate electrode of the first transistor, a dielectric layer, which is disposed on the gate electrode of the first transistor, and by a further conductive spacer, which is separated from the gate electrode of the first transistor by the dielectric layer. The Schottky diode is formed by a conductive structure made of metal silicide, which is disposed on an upper part of the further conductive spacer and adjoins the common source/drain region, and by the conductive spacer.
Published, European Patent Application EP 0 537 203 describes a DRAM cell configuration in which a memory cell contains a planar first transistor, a planar second transistor and a voltage-dependent resistor. The first transistor and the second transistor have a common source/drain region and are connected between a voltage terminal and a bit line. A gate electrode of the first transistor is disposed over a gate dielectric and a metal film is disposed over the common source/drain region. The common source/drain region is connected to the gate electrode of the first transistor via the voltage-dependent resistor. The voltage-dependent resistor is, for example, a Schottky junction and is formed by the gate electrode of the first transistor and the metal film. A gate electrode of the second transistor is connected to a word line. The voltage-dependent resistor does not require any additional space, which contributes to increasing the packing density of the DRAM cell configuration.
U.S. Pat. No. 5,463,234 discloses an integrated circuit configuration in which a Schottky diode is connected between a source/drain and a titanium film which extends over a gate electrode. Between the gate electrode and the titanium film there is a silicon film and a titanium silicide film. The titanium silicide film forms on the source/drain the Schottky diode that can, if appropriate, be replaced by a diode with a pn-type junction structure.
Furthermore, U.S. Pat. No. 5,710,448 discloses how a diode contact is to be implemented in such a way that an off-state current flows owing to tunnel processes.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an integrated circuit configuration and a method for manufacturing it which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which has a high packing density.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit configuration. The integrated circuit configuration contains a substrate having a main surface and a planar transistor having a first source/drain region and a second source/drain region disposed in the substrate and adjoining the main surface of the substrate. The planar transistor further has a gate electrode disposed above the substrate. A diode is connected between the first source/drain region and the gate electrode such that the diode makes it more difficult for a charge to flow away from the gate electrode to the first source/drain region. The diode has a diode layer containing an insulating material and is disposed on at least part of the first source/drain region. The diode layer has a thickness dimensioned such that a current through the diode layer is produced due to the tunneling of electrodes through the diode layer. The diode further has a conductive structure disposed over at least part of the gate electrode and on the diode layer.
An integrated circuit configuration contains a planar first transistor whose first source/drain region and whose second source/drain region are disposed in a substrate and adjoin a main surface of the substrate. A gate electrode of the first transistor is provided over the substrate. A diode is connected between the first source/drain region and the gate electrode in such a way that it is made more difficult for a charge to flow away from the gate electrode to the first source/drain region. A diode layer, which is part of the diode, is disposed on at least part of the first source/drain region.
A conductive structure, which is a further part of the diode, is disposed over at least part of the gate electrode and on the diode layer.
In a method for manufacturing an integrated circuit configuration, the first source/drain region and the second source/drain region of the planar first transistor are generated by masked implantation of the substrate, in such a way that they adjoin the main surface of the substrate. The gate electrode of the first transistor is formed above the substrate. A diode layer, which is part of the diode, is formed on at least part of the first source/drain region. The conductive structure, which is a further part of the diode, is formed in such a way that it is disposed over at least part of the gate electrode and on the diode layer. The diode is formed in such a way that it is made more difficult for a charge to flow away from the gate electrode to the first source/drain region.
Because the diode is disposed over the first transistor, the integrated circuit configuration can have a high packing density. In contrast to Published, European Patent Application EP 0 537 203, the first transistor can be manufactured in the same way as a transistor using currently customary semiconductor fabrication methods. The diode is manufactured only by the following process steps. The Schottky junction according to European Patent Application EP 0 537 203 must be partially generated before the completion of the transistor because the metal film is disposed under the gate electrode. In addition, the source/drain regions of the transistor according to EP 0 537 203 are not generated by implantation after the gate electrode is formed, as in the conventional method, because the gate electrode is disposed over a greater part of the first source/drain region on which the metal film is located. A further difference with respect to EP 0 537 203 consists in the fact that the gate electrode of the first transistor is not part of the diode so that, owing to the free selection of the material of the conductive structure, electrical properties of the diode can be optimized independently of the gate electrode.
If the integrated circuit configuration contains, in addition to the first transistor and the diode, a second (further) transistor whose first source/drain region is connected to the first source/drain region of the first transistor, the integrated circuit configuration can contain a DRAM cell configuration. The first transistor, the diode and the second transistor are parts of a memory cell of the DRAM cell configuration. The first transistor and the second transistor are connected between a voltage terminal and a bit line. A gate electrode of the second transistor is connected to a word line. The DRAM cell configuration is a dynamic self-amplifying memory cell configuration in this case.
The storage of a logic
Hofmann Franz
Krautschneider Wolfgang
Schlösser Till
Willer Josef
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Richards N. Drew
Stemer Werner H.
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