Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-07-12
2005-07-12
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C713S002000, C713S100000, C713S193000
Reexamination Certificate
active
06918103
ABSTRACT:
An integrated circuit containing a plurality of data processing circuit elements4, 6, 8, 10, 12, 14and16is provided with a configuration data memory12. Upon initialisation of the integrated circuit2, configuration data is read from the configuration data memory12and used to set up configuration program software26that controls the interaction between application program software18, 20, 22and the integrated circuit2. The configuration data is automatically formed from a human readable hierarchical description of the integrated circuit2in the form of an ASN.1 description.
REFERENCES:
patent: 5473546 (1995-12-01), Filseth
patent: 5745734 (1998-04-01), Craft et al.
patent: 5883814 (1999-03-01), Luk et al.
patent: 5970142 (1999-10-01), Erickson
patent: 6028445 (2000-02-01), Lawman
patent: 6216258 (2001-04-01), Mohan et al.
patent: 6272669 (2001-08-01), Anderson et al.
patent: 6305005 (2001-10-01), Burnham
patent: 6438737 (2002-08-01), Morelli et al.
patent: 6438738 (2002-08-01), Elayda
patent: 6487648 (2002-11-01), Hassoun
patent: 6510546 (2003-01-01), Blodget
patent: 6526558 (2003-02-01), Agrawal et al.
patent: 6557156 (2003-04-01), Guccione
patent: 6571381 (2003-05-01), Vorbach et al.
patent: 6584601 (2003-06-01), Kodosky et al.
patent: 6769109 (2004-07-01), Osann, Jr. et al.
patent: 2001/0034876 (2001-10-01), Panchul et al.
patent: 2001/0037458 (2001-11-01), Kean
patent: 2001/0047509 (2001-11-01), Mason et al.
patent: 2003/0005292 (2003-01-01), Matthews
patent: 2004/0133793 (2004-07-01), Ginter et al.
patent: 2 203 869 (1988-10-01), None
patent: 2 230 362 (1990-10-01), None
patent: 2 270 176 (1994-03-01), None
patent: 2346236 (1998-10-01), None
patent: 09282350 (1997-10-01), None
patent: 11085824 (1999-03-01), None
patent: WO 95/17714 (1995-06-01), None
patent: WO 99/14636 (1999-03-01), None
Zhu et al., “Hardware compilation for FPGA-based configurable computing machines”, Proceedings of 1999 Design Automatio Conference, Jun. 21, 1999, pp. 697-702.
Erdogan et al., “VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM”, Proceedings of the IEEE 1993 Custom Integrated Circuits Conference, May 9, 1993, pp. 3.3.1-3.3.4.
Akella et al., “SHILPA: a high-level synthesis system for self-timed circuits”, 1992 IEEE/ACM International Conference on Computer-Aided Design, Nov. 8, 1992, pp. 587-591.
Darby, “ASIC and FPGA design challenge”, IEE Colloquium on the Teaching of Digital Systems, May 18, 1998, pp. 1/1-1/3.
Yip et al., “Partial-encryption technique for intellual property protection of FPGA-based products”, IEEE Transactions on Consumer Electronics, vol. 46, No. 1, Feb. 2000, pp. 183-190.
Alphey James Roy
Brawn Jonathan William
ARM Limited
Kik Phallaka
Nixon & Vanderhye P.C.
Thompson A. M.
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