Electrical computers and digital processing systems: memory – Address formation – Varying address bit-length or size
Reexamination Certificate
1999-05-18
2002-07-23
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Varying address bit-length or size
C711S170000, C711S211000
Reexamination Certificate
active
06425066
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits and, more particularly, to an integrated circuit having at least two memories with different data formats.
BACKGROUND OF THE INVENTION
For microprocessor systems, several types of memories are commonly used. For example, a microcomputer may simultaneously have RAM, ROM, EPROM, EEPROM and Flash type memories. Naturally, these different types of memories may have different capacities and use different data formats corresponding to the function of each memory. Thus, in a given system, it is possible, for example, to have a flash memory with an 8 Mbit capacity whose data elements are organized in 8 bits while simultaneously having a 256 Kbit EEPROM whose data elements are organized in 8 bits. On the contrary, another system may require a flash memory with a capacity of 8 Mbits whose data is organized in 16 bits, while simultaneously requiring a 256 Kbit EEPROM type memory whose data elements are organized in 8 bits.
The maximum integration of circuits within a chip makes it possible to provide electronic systems with greater reliability and also tends to reduce their cost. If two different memories were integrated on the same chip, a silicon manufacturer can easily build two different integrated circuits. One circuit includes a flash memory organized in 8 bits, and the other circuit includes a flash memory organized in 16 bits. For the semiconductor manufacturer, it is preferable to manufacture a single circuit that can be used instead of these two circuits. This would serve the purpose of reducing costs and manufacturing time.
While there are known ways of making parallel access memories that can be configured in at least two different data formats, a problem arises when a configurable memory is coupled in the same circuit with at least one other memory that is non-configurable or configured independently. The two memories can be accessed by the same address bus. For a configurable memory, the address bus has a variable size depending on the configuration of the data format and, conventionally, the added address bit corresponds to a least significant bit.
Furthermore, if the memories have page (read or write) access systems, then all the address bits that address different words in the same page have to be assembled in least significant bits. The result of these constraints is that it is not possible to couple a memory that is configurable in two data formats with a second memory that would have page access and/or would be also configurable.
SUMMARY OF THE INVENTION
An object of the present invention is to resolve the problem of integrating at least two memories in an integrated circuit by having at least one of the memories configurable according to one of two data formats. To connect the two memories, at least one routing circuit is added for rerouting two, or two out of four address wires in the integrated circuit to address at least one of the memories as a function of the configuration of the configurable memory.
The integrated circuit includes at last one first memory that is configurable according to first and second data formats. A first format selection input determines the data format of the first memory. The integrated circuit further includes a second memory. An external address bus provides an address to the integrated circuit. A first internal bus is connected to the external address bus by a first rerouting circuit. The first rerouting circuit makes either a direct connection of the address bus with the first internal bus, or a connection between the address bus and the first internal bus by rerouting two wires from the external address bus so that they have different place values. This connection is dependent upon whether a signal is present at the first selection input which indicates that the first memory is operating with the first format or with the second format. The first internal bus is connected to an address input of one of the two memories.
REFERENCES:
patent: 5323356 (1994-06-01), Okunaga
patent: 5396608 (1995-03-01), Garde
patent: 5535342 (1996-07-01), Taylor
patent: 5737767 (1998-04-01), Agrawal et al.
patent: 0 337 457 (1989-04-01), None
Leconte Bruno
Moreaux Christophe
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Chace Christian P.
Jorgenson Lisa K.
Kim Matthew
STMicroelectronics S.A.
LandOfFree
Integrated circuit comprising at least two memories does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit comprising at least two memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit comprising at least two memories will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2819847