Integrated circuit chip with adaptive input-output port

Details Integrated circuit chip with adaptive input-output port Integrated circuit chip with adaptive input-output port

1996-06-26

1998-03-24

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 27, 326 86, H03K 1716

Patent

active

057317119

ABSTRACT:
A controllable impedance arrangement is used in an adaptable input-output port of an integrated circuit configuration to enable the port to advantageously adapt its impedance according to whether its transmitting or receiving a communication signal. The controllable impedance arrangement provides different specific impedances for transmitting signals at respective signal levels, or a terminating impedance when receiving a data signal. This impedance arrangement enables the input-output port and corresponding integrated circuit to have compact dimensions relative to conventional integrated circuits.

REFERENCES:
patent: 5194765 (1993-03-01), Dunlop et al.
patent: 5243229 (1993-09-01), Gabara et al.
patent: 5294845 (1994-03-01), McMahan et al.
patent: 5298800 (1994-03-01), Dunlop et al.
patent: 5481207 (1996-01-01), Crafts
patent: 5528168 (1996-06-01), Kleveland
patent: 5578939 (1996-11-01), Beers et al.
patent: 5596285 (1997-01-01), Marbot et al.
patent: 5621335 (1997-04-01), Andresen
patent: 5654895 (1997-08-01), Bach et al.
T.J. Gabara, "Ground Bounce Control in CMOS Integrated Circuits", Digest of technical Papers -IEEE International Solid-State Circuits Conference, pp. 88-89 (1988).
H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Ch. 6, pp. 226-274, (Addison-Wesley Publishing Co. 1990).
"High Speed Transceiver Logic (HSTL) -A 1.5 V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits", Electronic Industries Association, EIA/JEDEC Standard 8-6 (Aug. 1995).
B. Gunning et al. "A CMOS Low-Voltage-Swing Transmission-Line Transceiver, Digest of Technical Papers -IEEE International Solid-State Circuits conference", pp. 58-59 (1992).
"Gunning Transceiver Logic (GTL)-Low-Level, High-Speed Interface Standard for Digital Integrated Circuits", Electronic Industries Association, EIA/JEDEC Standard 8-3 (Nov. 1993).
T.J. Gabara et al. "Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers", IEEE 1996 Custom Integrated Circuits Conference, pp. 277-280.
M.S.J. Steyaert, et al. "ECL-CMOS and CMOS-ECL Interface in 1.2-.mu.m CMOS for 150-MHz Digital ECL Data Transmission Systems", IEEE Journal of Solid-State Circuits, vol. 26, No. 1, pp. 18-23 (1991).

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