Integrated circuit chip with a wide I/O memory array and redunda

Details Integrated circuit chip with a wide I/O memory array and redunda Integrated circuit chip with a wide I/O memory array and redunda

1996-11-26

1998-08-18

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518908, G11C 700

Patent

active

057966621

ABSTRACT:
An integrated circuit chip with RAM, a RAM macro or bit slice data logic and at least one spare array element or spare slice element and the redundancy scheme therefor. The chip includes a wide data path with a plurality of interchangeable elements such as bit slice elements or memory element and at least one more element than the number of bits in the wide data path; selection logic for deselecting defective data elements; and, switches for selectively coupling each bit of the wide I/O data path to one element or to an element adjacent the one element responsive to the selection means. The integrated circuit chip may further include drive means for selectively driving data from the switches to the element or, otherwise, passing data from the elements to the switches. The switches preferably are three-way switches, such as three CMOS pass gates.

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"Method to Reconfigure Logic Signal Paths", IBM Technical Disclosure Bulletin, V. 29, #4, pp. 1575-1578, Sep. 1986.
Improved Bit Sparing Technique Yields Faster Memory Array Access: IBM Technical Bulletin, V. 33, #11, pp. 92-95, Apr. 1991.
"Bit Sparing Logic for Semiconductor Memory Systems" IBM Technical Disclosure Bulletin, V. 37, #06A, pp. 361, 362, Jun. 1994.

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