Integrated circuit chip sealing assembly

Details Integrated circuit chip sealing assembly Integrated circuit chip sealing assembly

1988-03-01

1990-03-06

James, Andrew J.

357 74, H01L 2330, H01L 2348

Patent

active

049070657

ABSTRACT:
An integrated circuit (IC) chip package is formed by extending the overall dimensions of a standard IC on a semiconductor substrate, typically a first silicon wafer, to provide an integral band of semiconductor material therearound on which are formed a series of spaced IC chip input/output pad areas extending along the band. A bottom peripheral edge of a discrete cap of the same semiconductor material, e.g. silicon, is sealingly affixed around an inner periphery of the band inboard of the series of pad areas and outboard of the IC active circuit areas, so that the cap interior spacedly covers the active circuit area and the input/output pad areas are exposed. The caps may be made by photolithography and microetching techniques from a second semiconductor wafer of the same type as the IC wafer. Metallization extends on the first wafer from connect pads on the active circuit area to the extended and exposed input/output pad areas exterior of the cap. The IC may be probed for test purposes prior to capping. Use of lead frames, plastic encapsulation processes and a ceramic housing are avoided, while maximizing the use of compatible materials having the same coefficient of thermal expansion. In one embodiment, essentially an "all silicon" package is provided.

REFERENCES:
patent: 4355463 (1982-10-01), Burns
patent: 4398208 (1983-08-01), Murano et al.
patent: 4672418 (1987-06-01), Moran et al.
patent: 4731699 (1988-03-01), Nitta et al.
IBM Disclosure, "Ceramic Leaded Chip Carrier Capping Techniques", vol. 29, No. 2, Jul. 1986, pp. 916-918.

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