Integrated circuit chip having built-in self measurement for PLL

Details Integrated circuit chip having built-in self measurement for PLL Integrated circuit chip having built-in self measurement for PLL

1996-03-08

1997-09-02

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375226, H03D 324

Patent

active

056639910

ABSTRACT:
A built-in system and method is provided that measures Phase Lock Loop (PLL) output clock error. An edge sorting circuit is utilized to measure jitter between corresponding transition edges of a measured clock and a reference clock, and then stores the value in an N bit word. A decoder circuit reads in the value and increments a corresponding counter. A state machine then reads the counters, processes the information and outputs one or more PLL clock error values.

REFERENCES:
patent: 4363002 (1982-12-01), Fuller
patent: 4743857 (1988-05-01), Childers
patent: 4795985 (1989-01-01), Gailbreath, Jr.
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 4926447 (1990-05-01), Corsetto et al.

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