Integrated circuit chip design

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000

Reexamination Certificate

active

10231384

ABSTRACT:
Method of developing a model of a circuit design including the steps of generating four different path-tracing runs, creating four arcs from the four different path-tracing runs, and combining the four arcs into two separate models. Also, a method of adjusting timing of a clock signal provided to a first block and a second block where data signals travel via a first path from the first block to the second block and data signals travel via a second path from the second block to the first block and the time for the data signals to travel the first path is greater than the time for the data signals to travel the second path. The clock signal provided to the second block relative to the clock signal provided to the first block is delayed by an amount that is a function of the difference between the time for the data signals to travel the first path and the time for the data signals to travel the second path.

REFERENCES:
patent: 5258660 (1993-11-01), Nelson et al.
patent: 5259006 (1993-11-01), Price et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5507029 (1996-04-01), Granato et al.
patent: 5557779 (1996-09-01), Minami
patent: 5602754 (1997-02-01), Beatty et al.
patent: 5696771 (1997-12-01), Beausang et al.
patent: 5740347 (1998-04-01), Avidan
patent: 5768159 (1998-06-01), Belkadi et al.
patent: 5801958 (1998-09-01), Dangelo et al.
patent: 5896299 (1999-04-01), Ginetti et al.
patent: 5936867 (1999-08-01), Ashuri
patent: 5956257 (1999-09-01), Ginetti et al.
patent: 6009248 (1999-12-01), Sato et al.
patent: 6266803 (2001-07-01), Scherer et al.
patent: 6272667 (2001-08-01), Minami et al.
patent: 6311313 (2001-10-01), Camporese et al.
patent: 6484268 (2002-11-01), Tamura et al.
patent: 6539536 (2003-03-01), Singh et al.
patent: 6557151 (2003-04-01), Donath et al.
patent: 6584436 (2003-06-01), Hellestrand et al.
patent: 6594805 (2003-07-01), Tetelbaum et al.
patent: 6609233 (2003-08-01), Foltin et al.
patent: 6701505 (2004-03-01), Srinivasan
patent: 6711719 (2004-03-01), Cohn et al.
patent: 2001/0010090 (2001-07-01), Boyle et al.
patent: 2001/0034593 (2001-10-01), Cooke et al.
patent: 2002/0073380 (2002-06-01), Cooke et al.
patent: 2002/0162086 (2002-10-01), Morgan
patent: 2003/0033580 (2003-02-01), Cohn et al.
patent: 11-306218 (1999-11-01), None
patent: 2000-286342 (2000-10-01), None
T. Koga et al., “Mega-gate ASIC Implement design”, a technical report of IEICE, The Institute of Electronics, Information and Communication Engineers, vol. 98, No. 293, pp. 71-77 (Sep. 1998).

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