Integrated circuit chip and pass gate logic family therefor

Details Integrated circuit chip and pass gate logic family therefor Integrated circuit chip and pass gate logic family therefor

1994-12-20

1996-04-16

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326121, 326 17, 326 24, H03K 190948

Patent

active

055086411

ABSTRACT:
An integrated circuit chip with high level logic functions formed from a pass gate logic family. The logic for each logic book includes at least one pass gate. Each book has complementary outputs and a pseudo latch attached to its outputs. If the book is of one FET type, the pseudo latch is of the opposite type. Books are placed in the logic function such that the output pseudo latches redrive opposite logic levels on alternating stages of series-connected books.

REFERENCES:
patent: 4233524 (1980-11-01), Burdick
patent: 4620117 (1986-10-01), Fang
patent: 4646306 (1987-02-01), David et al.
patent: 4709346 (1987-11-01), Henlin
patent: 4710649 (1987-12-01), Lewis
patent: 4713790 (1987-12-01), Kloker et al.
patent: 4716312 (1987-12-01), Mead et al.
patent: 4798980 (1989-01-01), Sugiyama et al.
patent: 4888499 (1989-12-01), Sanwo et al.
patent: 4912665 (1990-03-01), Waller et al.
patent: 5015881 (1991-05-01), Chappell et al.
patent: 5039883 (1991-08-01), On
patent: 5126596 (1992-06-01), Millman
patent: 5155387 (1992-10-01), Fletcher et al.
patent: 5218246 (1993-06-01), Lee et al.
J. S. Hiltebeitel, CMOS XOR, IBM Technical Disclosure Bulletin, V. 27, #4B Sep. 1984, p. 2639.
M. R. Ouellette, et al, Fast Carry Sum Adder, IBM Technical Disclosure Bulletin, V. 30, #5, Oct. 1987, pp. 323-324.
K. Yano, et al., A 3.8-ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic, IEEE, 1990.
C. Heikes, A 4.5mm2 Multiplier Array For A 200MFlop Pipelined Coprocessor, Digest of Technical Papers, High-Performance Logic Circuit Techniques, Paper FA 18.1, Session 18, ISSCC94, pp. 290-291.
H. Partovi, et al., A Regenerative Push-Pull Differential Logic Family, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, High-Performance Logic Circuit Techniques, FA 18.3, Session 18, ISSCC94, pp. 294-295.

Affiliated with

Also associated with

Rating

Integrated circuit chip and pass gate logic family therefor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit chip and pass gate logic family therefor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit chip and pass gate logic family therefor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-327881