Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-02-22
2002-08-06
Jackson, Jr., Jerome (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S734000, C257S690000, C257S784000
Reexamination Certificate
active
06429514
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an integrated circuit chip and a method for fabricating the same, more particularly to an integrated circuit chip and a method for fabricating the same that can reduce production costs and that can increase production capacity.
2. Description of the Related Art
Referring to
FIGS. 1A
to
1
C, a conventional method for fabricating an integrated circuit chip is shown. As shown in
FIG. 1A
, a die
10
having an upper surface provided with a plurality of solder pads
100
is attached to a tie bar
130
on a lead frame
13
by means of a double-side adhesive tape
12
to fix the die
10
on the lead frame
13
. The solder pads
100
are exposed via a bore
1300
formed in the tie bar
130
, as shown in FIG.
1
D. Referring to
FIG. 1B
, each of the solder pads
100
is connected electrically to a respective lead
131
of the lead frame
13
via known wire bonding-techniques by means of a conductive wire
14
that extends through the bore
1300
. Referring to
FIG. 1C
, a plastic protective layer
15
is used to encapsulate the die
10
and a portion of the lead frame
13
to form an integrated circuit chip.
The following are some of the drawbacks of the conventional method for fabricating an integrated circuit chip:
1. The aforesaid method needs different kinds of lead frames for different kinds of packaging, such as TSOP, SOJ, QFP, SOP and so on. Thus, at least one mold is prepared for each customer, thereby increasing costs.
2. In the aforesaid method, double-side adhesive tape is needed to secure the die on the tie bar, thereby increasing the fabricating costs.
3. In the aforesaid method, it will take a long time to form the molds for the lead frames, thereby affecting the ability of manufacturers to compete.
SUMMARY OF THE INVENTION
Therefore, the main object of the present invention is to provide an integrated circuit chip and a method for fabricating the same which can overcome the drawbacks associated with the aforesaid prior art.
According to this invention, a method for fabricating an integrated circuit chip comprises:
(a) forming a circuit board unit with a die-receiving cavity, and a plurality of contact pads on a top surface of thee circuit board unit;
(b) forming a die having an upper surface provided with a plurality of solder pads;
(c) placing the die in the die-receiving cavity such that the solder pads on the die are exposed;
(d) wire-bonding the solder pads to the contact pads via conductive wires;
(e) placing a lead frame on the circuit board unit, and connecting leads on the lead frame to corresponding ones of the contact pads via a conductive contact layer; and
(f) forming a plastic protective layer to encapsulate the circuit board unit and at least a portion of the lead frame.
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Computech International Ventures Limited
Cruz Lourdes
Jackson, Jr. Jerome
Marshall & Melhorn LLC
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