Static information storage and retrieval – Systems using particular element – Semiconductive
Reexamination Certificate
2000-02-15
2001-04-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Semiconductive
C365S230060, C365S230080
Reexamination Certificate
active
06212095
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to charge pump coupling circuitry.
BACKGROUND OF THE INVENTION
Charge pumps are well known in the art as an on-chip voltage regulator capable of providing a voltage more positive than the most positive external power supply voltage and/or negative voltage in the absence of a negative power supply voltage. The pump voltage is provided by a charge stored on a charge capacitor. The advantages of charge pumps are also well known in the art, for example, such as providing a bias voltage for the substrate of an integrated circuit or n-type and p-type wells, or for providing greater output voltage swings.
Many types of integrated circuit memories require several different power levels for operation. Some of these power levels exceed the available potential range of the external power supplies used to power the circuit. For example, access transistors connected to dynamic memory cells typically use a pumped voltage (Vccp) to drive their gates above the most positive power supply voltage. The Vccp is typically provided by a charge pump and is used to allow a complete charge to be written to the memory cell. If a lower voltage were used as the gate potential, such as the supply voltage Vcc, a threshold voltage (Vt) would be lost between the source and drain, such that a full source voltage could not reach the drain. Further, a charge pump is typically employed in non-volatile memory systems, such as flash memory systems, to provide voltages required for programming and erasing memory cells in a non-volatile memory.
Most charge pumps use an oscillator circuit, such as a ring oscillator, to provide a square wave or pulse train having voltage swings typically between ground and the most positive external supply voltage, Vcc. The pumped voltage level is partially controlled by the ring oscillator. That is, the pumped charge is generated when the ring oscillator cycles high. The ring oscillator, therefore, has an active half-cycle and an inactive half-cycle. A charge capacitor is typically pre-charged during the inactive half-cycle. The capacitor charge is then pumped to a higher level by charge sharing with another capacitor when the ring oscillator transitions to the active half-cycle. To reduce the amount of inactive time, charge pumps can have more than one phase where each phase operates on either the high or low transition of the ring oscillator.
A charge pump typically includes several pump stages which each include a pump capacitor which is charged and discharged during a clock cycle of the charge pump. A stage diode is coupled between the pump capacitor and the stage input voltage to prevent discharging of the pump capacitor prior to the pump capacitor having additional charge placed on it. Thus, a charge pump progressively stores more charge on the capacitor component of each stage, and several such stages being placed together in the charge pump produce an increasing voltage level. In integrated circuits, the diode and the capacitor are typically formed from properly configured transistors.
One or more clock signals typically trigger the charging of the pump capacitors. A typical clock signal has a clock frequency with a time period somewhat less than the discharge time of the pump capacitors. In one such design, two clock signals having opposite phase trigger the charging of alternate stages of a multi-stage charge pump. The opposite phase clock signals in this design permit increasing the amount of charge which can be placed on the pump capacitors.
A conventional pump circuit
20
is illustrated generally in schematic diagram form in FIG.
1
A. Pump circuit
20
receives an input supply voltage on a line
22
. A first clock signal Ph
1
is received on a line
24
and a second clock signal Ph
2
having the opposite phase of clock signal Ph
1
is received on a line
26
.
FIG. 1B
illustrates typical square wave clock signals Ph
1
and Ph
2
in timing diagram form. As illustrated in
FIG. 1B
, clock signals Ph
1
and Ph
2
have opposite phases and amplitudes corresponding to the amplitude to the input supply voltage on line
22
. The input supply voltage on line
22
provides the initial supply of charge for pump circuit
20
.
Pump circuit
20
includes N pump stages, as represented by a first pump stage
28
and a second pump stage
30
. Clock signal Ph
1
is coupled to the first pump stage
28
and clock signal Ph
2
is coupled to the second pump stage
30
. Similarly, clock signals Ph
1
and Ph
2
are alternately coupled to the remaining N-
2
pump stages of pump circuit
20
. Each of the N pump stages comprise a stage transistor figured to function as a diode, such as indicated at
32
a
for first pump stage
28
and at
32
b
for second pump stage
30
. Each pump stage also includes a pump capacitor, such as indicated at
34
a
for pump stage
28
and at
34
b
for pump stage
30
. Stage transistors
32
a
and
32
b
are typically configured to act as diodes by connecting the gate of the transistor to its drain. Pump capacitor
34
a
is coupled between clock signal Ph
1
and the first stage output node VS
1
and pump capacitor
34
b
is coupled between clock signal Ph
2
and the second stage output node VS
2
.
The N pump stages are connected in a serial manner to eventually produce an Nth stage output voltage on a line
40
. The Nth stage output voltage is provide to an output transistor
42
. Output transistor
42
is configured to act as a diode by connecting its gate to its drain and provides a pump output voltage on a line
44
.
A capacitive load
50
is coupled to the charge pump via diode connected transistor
42
. The load is shown as a capacitor to emphasize the essentially capacitive nature of the load. A disadvantage of using the diode coupled transistor
42
as an isolation device is a decrease load voltage due to a voltage drop across the transistor. Under a back bias condition, a voltage drop of 2-3 volts can be experienced. As a result, an integrated circuit charge pump must be designed to produce a higher voltage on its last stage than the resultant voltage desired on the load. Because of processing technology constraints, such as junction breakdown, designing a charge pump to produce a higher output voltage is not always possible.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a coupling circuit which allows a charge pump to be designed without the need for an elevated output voltage.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. An integrated circuit is described which includes a charge pump circuit coupled to a capacitive load via a resistive coupling circuit.
In particular, the present invention describes a flash memory device comprising an array of non-volatile memory cells comprising a plurality of substantially capacitive word lines for accessing the memory cells, a charge pump for producing a output voltage selectively coupled to the plurality of word lines, and a diodeless coupling resistor circuit connected between a capacitive output of the charge pump and decode circuitry coupled to the plurality of word lines for producing a word line voltage
In another embodiment, a memory device comprising a charge pump comprising a plurality of series coupled capacitive stages for producing an output voltage which is greater than an input voltage of the charge pump, a capacitive load circuit coupled to an output of the charge pump, and a coupling circuit connected to the output of the charge pump and the capacitive load circuit. The coupling circuit comprising a diodeless coupling circuit connected to the output of the charge pump and the capacitive load circuit. The coupling circuit compris
Le Thong
Micro)n Technology, Inc.
Nelms David
Schwegman Lundberg Woessner & Kluth P.A.
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