Integrated circuit carrier

Details Integrated circuit carrier Integrated circuit carrier

2000-10-20

2004-03-23

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S737000

Reexamination Certificate

active

06710457

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit packages. More particularly, the invention relates to an integrated circuit carrier for an integrated circuit package.
BACKGROUND TO THE INVENTION
Due to the ever-increasing number of connections (pincount) of integrated circuits, the use of ball grid array packages to connect integrated circuits to printed circuit boards is increasing. This facilitates the redistribution of a very fine pitch of flip-chip bump array of the integrated circuit to a much larger pitch ball grid array for attachment to the printed circuit board (PCB).
The carrier is often referred to as an interposer and can be fabricated from different materials such as ceramic, or a plastics material such as bismaleimide triazine (BT).
The carrier also functions as a heat sink by removing thermal energy from the integrated circuit by thermal conduction. Accordingly, the carrier is subjected to thermal strains.
In addition, an electronic package assembly comprising the integrated circuit, the carrier and the PCB has a number of different materials with different mechanical properties. Complex thermal stresses can occur inside the package during operation due to non-uniform temperature distributions, geometry, material construction and thermal expansion mismatches.
Typically, these days the integrated circuit is electrically connected to the carrier by a ball grid array of gold or solder bumps. Similarly, the carrier is electrically connected to the PCB by a further, larger ball grid array of solder balls. The thermo-mechanical stresses are typically severest at the solder ball interfaces between the PCB and the carrier. This can result in shearing of the solder ball connection. The problem is amplified by an increase in edge length of the carrier because of an increase in the thermal strain differences between the PCB and the carrier. An increase in edge length of the carrier is typically associated with an increase in the number of integrated circuit connections and solder balls.
Current ball grid array design is, presently, at the limit of reliability for typical integrated circuit pin counts.
Typically, a solder ball has a peak elastic shear strain value of around 0.08%. Computational experiments done by the applicant using a 500 micron thick solid Silicon carrier, 500 micron diameter solder balls at 1 millimeter pitch, a 700 micron thick PCB and a 16 millimeter side silicon chip indicated a peak shear strain value of 1.476% in the outermost ball of the package which is far above the plastic yield value of the solder ball.
This result is to be expected as the balls at the outermost edge of the package experience the greatest amount of translational shear.
As indicated in the publication of the Assembly and Packaging Section of the International Technology Road Map for Semiconductors,—1999 Edition, the most recent edition available at the time of filing the present application, in Table
59
a
at page 217, a pin count of a high performance integrated circuit has of the order of 1800 pins. The technology requirements in the near term, i.e. until the year 2005 indicate that, for high performance integrated circuits, a pin count exceeding 3,000 will be required for which, as the table indicates, there is, to date, no known solution. Similarly, in Table
59
b
of that publication, at page 219, in the longer term, until approximately the year 2014, a pin count for high performance integrated circuit packages of the order of 9,000 will be required. Again, as indicated in the table, there is no known solution for this type of package.
These aspects are the focus of the present invention.
SUMMARY OF THE INVENTION
According to the invention, there is provided an integrated circuit carrier which includes
a receiving zone including electrical contacts for receiving an integrated circuit;
a plurality of island-defining portions arranged about the receiving zone, at least one island-defining portion having an electrical terminal electrically connected to one of the contacts of the receiving zone; and
a rigidity-reducing arrangement connecting each island-defining portion to each of its neighboring island-defining portions.
The carrier may be fabricated from a wafer of a non-conductive material. Preferably, to reduce thermal mismatch between the carrier and the integrated circuit, the wafer is of the same material as the integrated circuit to have a co-efficient of thermal expansion approximating that of the integrated circuit.
The island-defining portions and the rigidity-reducing arrangements may be formed by etching the wafer. Preferably, the etch is a re-entrant etch.
Each rigidity-reducing arrangement may be in the form of a serpentine member. The serpentine member may comprise one or a plurality of substantially parallel arms. In the case of a parallel arm arrangement, adjacent parallel arms may be interconnected by an orthogonal bridging portion.
Each of those island-defining portions bordering the receiving zone may be connected to the receiving zone by a secondary rigidity-reducing arrangement. The secondary rigidity-reducing arrangement may comprise a zig-zag element.
The electrical terminal of each island-defining portion may be in the form of a metal pad.


REFERENCES:
patent: 6078505 (2000-06-01), Turudic
patent: 2349014 (2000-10-01), None
patent: 11-284029 (1999-10-01), None
patent: 11-345826 (1999-12-01), None
patent: 2001-094228 (2001-04-01), None

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