Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-30
2001-09-18
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S309000, C257S532000
Reexamination Certificate
active
06291848
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices, and, more particularly, to a capacitor.
BACKGROUND OF THE INVENTION
Capacitors are used extensively in electronic devices for storing an electric charge. A capacitor includes two conductive plates or electrodes separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, depends upon the area of the plates, the distance between them, and the dielectric value of the insulator. Capacitors may be formed within a semiconductor device, such as, for example, a dynamic random access memory (DRAM) or an embedded DRAM.
As semiconductor memory devices become more highly integrated, the area occupied by the capacitor of a DRAM storage cell shrinks, thus decreasing the capacitance of the capacitor because of its smaller electrode surface area. However, a relatively large capacitance is desired to prevent loss of stored information. Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, which achieves both high cell integration and reliable operation.
One technique for increasing the capacitance while maintaining the high integration of the storage cells is directed toward the shape of the capacitor electrodes. In this technique, the polysilicon layer of the capacitor electrodes may have protrusions, fins, cavities, etc., to increase the surface area of the capacitor electrode, thereby increasing its capacitance while maintaining the small area occupied on the substrate surface.
Instead of forming the capacitor on the substrate surface, capacitors are also formed above the substrate, i.e., they are stacked above the substrate. The surface area of the substrate can then be used for forming transistors. With respect to increasing the capacitance of a stack capacitor, U.S. Pat. No. 5,903,493 to Lee discloses a capacitor formed above a tungsten plug. The surface area of the capacitor is increased by etching a trench in the dielectric layer around the tungsten plug. The tungsten plug interfaces with an underlying interconnection line, thus allowing different layers formed above the substrate to be connected.
The trench is patterned by conventional etching or other suitable techniques. The fundamental limit on how far the trench can be etched is determined by how well the tungsten plug is anchored or secured within the dielectric layer. Typically, the depth of the trench is limited to about one half the thickness of the dielectric layer. After the trench has been etched, a capacitor is formed above the tungsten plug. Unfortunately, if the trench is etched beyond one half the thickness of the dielectric, the tungsten plug is more likely to become loose and fall out. This physical separation between the tungsten plug and the underlying metal interconnection with the interconnection line can cause open circuits to be formed resulting in complete failure of the device or circuit incorporating the capacitor.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to increase the capacitance of a capacitor without reducing the reliability thereof.
This and other advantages, features and objects in accordance with the present invention are provided by an integrated circuit capacitor comprising a substrate, a first dielectric layer adjacent the substrate and having a first trench therein, and a first metal plug extending upwardly into the first trench. An interconnection line overlies the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. A second dielectric layer is on the interconnection line and has a second trench therein. A second metal plug extends upwardly into the second trench. More particularly, the second metal plug includes a body portion extending upwardly into the second trench, and anchor portions connected to the body portion and engaging the anchoring recesses to anchor the second metal plug to the interconnection line. The body portion and the anchor portions are preferably formed as a monolithic unit.
An important feature of the present invention is that the first metal plug preferably extends upwardly in a medial portion of the first trench so that the interconnection line overlies the first trench and contacts the first metal plug defining the anchoring recesses on opposite sides thereof. The first trench thus provides the anchoring recesses when the interconnection line is formed. In other words, the resulting topography of the interconnection line adjacent the first metal plug creates the anchoring recesses for the second metal plug. This is advantageously done without having to perform additional processing steps for forming equivalent recesses directly within the conductor portion of the interconnection line.
Because the second metal plug is anchored, a depth of the second trench can be greater without the second metal plug becoming loose and separating from the underlying interconnection line. If this were to occur, an open circuit would occur resulting in failure of the device or circuit incorporating the integrated circuit capacitor. The anchoring recesses formed on opposite sides of the second metal plug allows the depth of trench to be increased to thereby increase the capacitance, and without reducing the reliability of the integrated circuit capacitor.
The capacitor also preferably includes first and second electrodes and a third dielectric layer therebetween. The first electrode lines the trench and contacts the second metal plug. The third dielectric layer overlies the first electrode, and the second electrode overlies the third dielectric layer. Increasing the depth of the second trench in accordance with the present invention increases the surface area of the first and second electrodes. This advantageously increases the capacitance of the capacitor, which is desired for preventing a loss of stored information.
REFERENCES:
patent: 5903493 (1999-05-01), Lee
patent: 5976981 (1999-11-01), Cheng
patent: 6103586 (2000-08-01), Chetlur et al.
patent: 97/15950 (1997-01-01), None
Chetlur Sundar Srinivasan
Clemens James Theodore
Merchant Sailesh Mansinh
Roy Pradip Kumar
Vaidya Hem M.
Agere Systems Guardian Corp.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Prenty Mark V.
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