Integrated circuit capacitor and memory

Details Integrated circuit capacitor and memory Integrated circuit capacitor and memory

1998-06-26

2003-07-29

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S310000

Reexamination Certificate

active

06600183

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to electronic devices, and more specifically to semiconductor integrated circuit capacitors and methods of fabrication.
BACKGROUND OF THE INVENTION
Increasing demand for semiconductor memory and competitive pressures require higher density integrated circuit dynamic random access memories (DRAMs) based on one-transistor, one-capacitor memory cells. But scaling down capacitors with the standard silicon oxide and nitride dielectric presents problems including decreasing the quantity of charge that may be stored in a cell. Consequently, alternative dielectrics with dielectric constants greater than those of silicon oxide and nitride are being investigated. Various dielectric materials are available, such as tantalum pentoxide (dielectric constant about 25 versus silicon nitride's dielectric constant of about 7) as described in Ohji et al., “Ta
2
O
5
capacitors' dielectric material for Giga-bit-DRAMs,” IEEE IEDM Tech. Dig. 5.1.1 (1995); lead zirconate titanate (PZT), which is a ferroelectric and supports nonvolatile charge storage (dielectric constant of about 1000), described in Nakamura et al., “Preparation of Pb(Zr,Ti)O
3
thin films on electrodes including IrO
2
, 65 Appl. Phys. Lett. 1522 (1994); strontium bismuth tantalate (also a ferroelectric) described in Jiang et al. “A New Electrode Technology for High-Density Nonvolatile Ferroelectric (SrBi
2
Ta
2
O
9
) Memories,” VLSI Tech. Symp. 26 (1996); and barium strontium titanate (dielectric constant about 500), described in Yamamichi et al., “An ECR MOCVD (Ba,Sr)TiO
3
based stacked capacitor technology with RuO
2
/Ru/TiN/TiSi
x
storage nodes for Gbit-scale DRAMs,” IEEE IEDM Tech. Dig. 5.3.1 (1995), Yuuki et al., “Novel Stacked Capacitor Technology for 1 Gbit DRAMs with CVD-(Ba,Sr)TiO
3
Thin Films on a Thick Storage Node of Ru,” IEEE IEDM Tech. Dig. 5.2.1 (1995), and Park et al., “A Stack Capacitor Technology with (Ba,Sr)TiO
3
Dielectrics and Pt Electrodes for 1 Giga-Bit density DRAM, VLSI Tech. Symp. 24 (1996). Also see Dietz et al., “Electrode influence on the charge transport through SrTiO
3
thin films, 78 J. Appl. Phys. 6113 (1995), (describes electrodes of Pt, Pd, Au, and so forth on strontium titanate); U.S. Pat. No. 5,003,428 (PZT and barium titanate), U.S. Pat. No. 5,418,388 (BST, SrTiO
3
, PZT, etc.), and U.S. Pat. No. 5,566,045 (thin Pt on BST).
These alternative dielectrics are typically deposited at elevated temperatures and in an oxidizing ambient. As a result, an oxygen-stable bottom electrode material such as platinum or ruthenium oxide is used. Platinum, however, readily forms a silicide when in direct contact with silicon, and further is not a good barrier to oxygen due to fast diffusion down the platinum grain boundaries. In U.S. Pat. No. 5,504,041, Summerfelt uses a conductive nitride barrier layer beneath a platinum electrode to inhibit diffusion of oxygen to an underlayer susceptible to oxidation. Another problem with platinum electrodes is that the adhesion of platinum to silicon dioxide, silicon nitride, and other common interlayer dielectric materials is poor. Platinum structures that are patterned and etched tend to debond during subsequent processing. U.S. Pat. Nos. 5,489,548; 5,609,927; and 5,612,574 propose the use of an adhesion layer to prevent the debonding of the platinum electrode.
Some of these alternative dielectrics, such as PZT, BST, and SBT are ferroelectrics, and hence may be used as the storage element in ferroelectric non-volatile RAMs (FRAM). An FRAM cell is similar to a DRAM cell, except that the polarization of the ferroelectric material is used to indicate the data content of the cell in an FRAM, while electrical charge in the material indicates the data content of the cell in a DRAM. The charge in the DRAM dissipates, while the polarization of the material is non-volatile.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the invention, there is disclosed an electrode structure for a capacitor. The electrode structure includes a contact plug comprising an oxidation barrier and a bottom electrode comprising a conductive adhesion-promoting portion and an oxidation-resistant portion, the adhesion-promoting portion contacting the oxidation barrier of the contact plug. In further embodiments, the oxidation barrier and adhesion-promoting portion comprise Ti—Al—N.
In accordance with another preferred embodiment of the invention, there is disclosed a capacitor. The capacitor includes a bottom electrode having a conductive adhesion-promoting layer at a first surface; a storage layer in contact with a second surface of the bottom electrode; a top electrode in contact with the storage layer; and a contact plug connected to the bottom electrode by the adhesion-promoting layer, the contact plug comprising a barrier adjacent the adhesion-promoting layer.
In accordance with still another preferred embodiment of the invention, there is disclosed a memory circuit including a memory cell. The memory cell includes a capacitor including a bottom electrode having a conductive adhesion-promoting layer at a first surface; a storage layer in contact with a second surface of the bottom electrode; and a top electrode in contact with the storage layer. The memory cell also includes a transistor comprising first and second terminals and a wordline control terminal; and a bitline coupled to said first transistor terminal. The bottom electrode is coupled to the second transistor terminal by a plug comprising a barrier adjacent the adhesion-promoting layer, the barrier being thicker than the adhesion-promoting layer.
An advantage of the inventive concepts is that a platinum electrode can be made to adhere to an interlayer dielectric, while also allowing for a recessed oxidation barrier to prevent oxidation at the barrier/electrode interface.


REFERENCES:
patent: 5231306 (1993-07-01), Meikle et al.
patent: 5360995 (1994-11-01), Graas
patent: 5382817 (1995-01-01), Kashihara
patent: 5504041 (1996-04-01), Summerfelt
patent: 5609927 (1997-03-01), Summerfelt et al.
patent: 5679969 (1997-10-01), Evans, Jr. et al.

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