Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-04-25
2006-04-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07036099
ABSTRACT:
An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
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patent: 6411116 (2002-06-01), DeHaven et al.
patent: 6426904 (2002-07-01), Barth et al.
patent: 6618830 (2003-09-01), Balachandran et al.
Cheng An-Ru Andrew
Lin Chang-Song
Liu Tzu-Chun
Tseng Huan-Yung
Faraday Technology Corp.
Hsu Winston
Levin Naum
Siek Vuthe
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