Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-10-17
2003-07-01
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S775000, C257S207000, C257S664000, C257S692000, C257S923000
Reexamination Certificate
active
06586828
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of microelectronics. More particularly, the present invention is directed to an integrated circuit bus grid having wires with pre-selected variable widths.
2. Background of the Invention
A large portion of the semiconductor industry is presently devoted to the design and manufacture of application specific integrated circuit chips, or ASIC chips, which are used in many diverse applications, such as devices containing embedded systems. Examples of such devices include computers, cellular telephones, PDAs, thin clients, televisions, radios, domestic appliances, e.g., digital microwave ovens, dishwashers, clothes dryers and the like, automobiles, digital manufacturing, testing and diagnostic equipment and virtually every other digital device for consumer or industrial use. Frequently, ASICs designed for different applications contain many of the same basic logic, memory and I/O elements, or cells, as one another. However, for different applications these cells may be present in different numbers, arranged differently and have different interconnectivity, among other differences. Examples of cells include RAM, I/O, adder, clock, latches and communication ports, among others.
Since cell designs are often used repeatedly in creating new ASICs, manufacturers have built libraries of cells. When designing a new ASIC, the manufacturer may then retrieve the necessary cells from the library and combine them with one another, and perhaps with custom-designed cells, in the manner needed for a particular application. Important purposes of creating libraries containing standard cells are to reduce the cost of designing and manufacturing ASIC chips and simplify the process of designing ASICs.
In a further effort to reduce costs and simplify the design process, manufacturers often complement their cell libraries by standardizing other features of ASIC chips. For example, manufacturers often standardize the type and arrangement of electrical contacts, i.e., power, ground and I/O contacts, for interfacing a completed chip with packaging and standardize the power and ground buses that provide, respectively, power and grounding to the microelectronic devices, e.g., transistors, that make up the various cells.
FIGS. 1
,
1
A,
2
and
3
show a particularly useful standardized arrangement of electrical contacts and power and ground buses in connection with an exemplary ASIC die
10
.
Referring to
FIG. 1A
, ASIC die
10
includes at its surface two interposed rectangular area arrays of power contacts
12
(e.g., VDD, VDDx) and ground contacts
14
(e.g., GND, Vref), which are shown as comprising solder balls for controlled collapse chip connection (C
4
), or flip-chip, connectivity with a package (not shown). As one skilled in the art will readily appreciate, electrical connectivity of power and ground contacts with a package may be alternatively effected using another technique, such as wire bonding. Also shown is a rectangular area array of I/O contacts
16
interposed with power contacts
12
and ground contacts
14
. Such area arrays of contacts
12
,
14
,
16
allow ASIC designers to place in the X-Y plane the necessary cells, e.g., RAM cell
18
, I/O cells
20
, and communication port cells
22
, wherever desired on die
10
such that the cells are always relatively proximate the appropriate contact(s).
FIG. 2
shows an electrical bus
11
coupling power contacts
12
with a device layer
24
. Electrical bus comprises seven metal layers, M
1
-M
7
, interleaved with insulating layers, I
1
-I
7
. One skilled in the art will appreciate that the number of metal layers and insulating layers shown is for illustrative purposes only. More or fewer than seven metal layers and corresponding insulating layers may be provided. Ground contacts
14
, I/O contacts
16
of FIG.
1
A and associated wiring are not shown for clarity. However, one skilled in the art will understand that the electrical interconnection between ground contacts
14
and device layer
24
may be similar to the interconnection of power contacts
12
with device layer
24
. Similarly, one skilled in the art will understand that I/O contacts
16
will be electrically interconnected with device layer
24
as necessary for the particular arrangement of I/O cells
20
.
FIG. 3
shows metal layers M
6
and M
7
as forming, in plan view, a rectangular bus grid
26
comprising conductive strips, or wires
28
,
30
, present within each of a plurality of contiguous regions
32
defined by the rectangular area array of power contacts
12
. Importantly, wires
28
have the same widths as one another and wires
30
have the same widths as one another. Referring now to
FIGS. 2 and 3
, metal layer M
6
contains wires
28
extending in the Y-direction and metal layer M
7
contains wires
30
extending in the X-direction. Wires
30
located directly beneath power contacts
12
are electrically connected to the power contacts by metal studs
34
extending through insulating layer
17
. Wires
28
in metal layer M
6
are electrically connected to wires
30
in metal layer M
7
by metal studs
36
at each location that wires
28
cross under wires
30
. As one skilled in the art will appreciate, metal layers M
5
to M
1
are similar to metal layers M
7
and M
6
but contain progressively finer wires. Wires
38
of metal layer M
1
are closely spaced from one another so that each device in device layer may be electrically connected thereto.
Providing area arrays of power and ground contacts and providing uniform power and ground grids in the metal layers permit designers to lay out the power and ground buses prior to arranging the cells in the device layer. Thus, the power and ground buses may be standardized, in large part eliminating the need to custom design these buses for each new ASIC design. Presently, ASIC designers typically arrange the wires within the same metal layer in a uniform pattern and typically provide the wires within the same metal layer with the same widths. For example, wires
28
of metal layer M
6
may be arranged as shown, and each wire will have the same width as the other wires
28
in metal layer M
6
. Similarly, wires
30
of metal layer M
7
may be arranged as shown, and each wire will have the same width as the other wires
30
in metal layer M
7
. The width of the wires is generally based upon the maximum possible current in the corresponding metal layer. Providing such uniform widths for the wires of the same metal layer, particularly the first two metal layers, e.g., metal layers M
7
and M
6
in the example of
FIGS. 2 and 3
, immediately below the power and ground contacts, however, wastes metal and takes up valuable space that an ASIC designer could otherwise use for signal and I/O wire routing. The limited amount space available in the metal layers for signal and I/O wire routing can require an ASIC designer to provide additional metal layers that are undesirable, particularly from a cost standpoint.
BRIEF SUMMARY OF THE INVENTION
In one aspect, the present invention is directed to an integrated circuit comprising a plurality of cells and an electrical bus in electrical communication with the plurality of cells. The electrical bus is designed using a current distribution modeled prior to arrangement of the plurality of cells. The electrical bus comprises a region and a first metal layer containing a plurality of first wires extending in a first direction. Each of the plurality of first wires has a first width at least partially located within the region. The first widths vary as a function of the current distribution.
In another aspect, the present invention is directed to a method of laying out an electrical bus grid for an integrated circuit having a plurality of regions. The method comprises in sequence the following steps. First, at least a plurality of first wires of a first metal layer are arranged in at least one of the plurality of regions, wherein each of the plurality of first wires has a first width
Buffet Patrick H.
Sun Yu H.
Clark Jasmine J B
Downs Rachlin & Martin PLLC
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