Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1999-09-14
2001-05-01
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000
Reexamination Certificate
active
06225838
ABSTRACT:
RELATED APPLICATION
This application is related to Korean Application No. 98-39099, filed Sep. 21, 1999, the disclosure of which is hereby incorporated herein by reference.
1. Field of the Invention
The present invention relates to integrated circuit devices, and more particularly to integrated circuit buffers.
2. Background of the Invention
Systems embodying integrated circuit devices frequently include a plurality of large scale integration (LSI) devices that operate at different power supply voltages. Because such devices are frequently electrically interconnected, input buffers are frequently provided within these devices to perform level-shifting operations. For example, input buffers may be provided within these devices to convert signals generated by LSI devices operating at TTL power supply voltages (e.g., 5 volts) into signals that are compatible with LSI devices operating at CMOS power supply voltages (e.g., 3.3 volts). A block diagram of a conventional integrated circuit device having LSI devices therein that operate at different supply voltages is illustrated by FIG.
1
. In particular,
FIG. 1
illustrates a first LSI device
10
that operates at a power supply voltage level of 5 volts and a second LSI device
12
that operates at a power supply voltage level of 3.3 volts and receives data from the first LSI device
10
. U.S. Pat. Nos. 5,654,664 to Park et al. and 5,543,733 to Mattos et al. also disclose conventional buffer circuits.
Referring now to
FIG. 2
, a conventional input buffer circuit
18
will be described. As illustrated, the buffer circuit
18
receives input data at an input pad
14
and generates output data to an output pad
16
. An input pass transistor MN
1
(e.g., NMOS transistor) is electrically connected in series (source-to-drain) between the input pad
14
and an input node
15
of an inverter comprising a PMOS pull-up transistor MP
1
and an NMOS pull-down transistor MN
2
. A CMOS power supply voltage V
DDL
of 3.3 volts, for example, may be provided to the gate electrode of the input pass transistor MN
1
. As will be understood by those skilled in the art, the magnitude of the largest logic 1 signal at the input node
15
will be equal to V
DDL
−Vth
MN1
, where Vth
MN1
is the threshold voltage of the input pass transistor MN
1
. Accordingly, the input buffer circuit
18
can be used to level shift TTL level signals (e.g., 5 volts) to CMOS level signals (e.g., 3.3 volts). Unfortunately, as illustrated by the downward arrow, leakage current will flow from the power supply signal line V
DDL
to the ground reference signal line V
ss
when a logic 1 level signal is present at the input node
15
. This leakage current will increase the static power consumption requirements of the buffer circuit. The magnitude of this leakage current is generally a direct function of the magnitude of the negative gate-to-source voltage across the PMOS pull-up transistor MP
1
. In particular, because the gate-to-source voltage across the PMOS pull-up transistor MP
1
may have a negative value of −Vth
MN1
when a logic
1
signal is present at the input node
15
, the PMOS pull-up transistor MP
1
may be turned on slightly whenever the output pad
16
is being pulled down to a logic 0 level by the NMOS pull-down transistor MN
2
.
Referring now to
FIG. 3
, another conventional input buffer circuit
24
will be described. The buffer circuit
24
receives input data at an input pad
20
and generates output data to an output pad
22
. An input pass transistor MN
3
(e.g., NMOS transistor) is electrically connected in series (source-to-drain) between the input pad
20
and an input node of an inverter comprising a PMOS pull-up transistor MP
2
and an NMOS pull-down transistor MN
4
. To reduce static leakage currents when the NMOS pull-down transistor MN
4
is turned on to pull down the output pad
22
to a logic 0 level, the input node is pulled up to V
DDL
by the PMOS pull-up transistor MP
3
. This operates to reduce the magnitude of the negative gate-to-source voltage across the PMOS pull-up transistor MP
2
and thereby reduce static leakage currents. Unfortunately, when the input pad
20
is being driven from a logic 0 level to a logic
1
TTL level that is greater than V
DDL
, some driving current may be transferred to the CMOS power supply signal line V
DDL
, along the current path illustrated by the arrow. If this driving current is present, the fan-out capability of the device (e.g., TTL LSI device
10
in
FIG. 1
) providing the input signal may be reduced.
Thus, notwithstanding the above-described conventional input buffers, there continues to be a need for input buffers that can perform a TTL-to-CMOS level shifting function and have reduced susceptibility to static leakage currents.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved integrated circuit buffers.
It is another object of the present invention to provide integrated circuit buffers that can perform TTL-to-CMOS level-shifting operations.
It is still another object of the present invention to provide integrated circuit buffers that can have reduced susceptibility to static leakage currents.
It is yet another object of the present invention to provide integrated circuit buffers that can have symmetric transfer characteristics.
These and other objects, advantages and features of the present invention are provided by integrated circuit buffers that include an inverter and a power supply control circuit that selectively powers the inverter at a first potential (e.g., V
DDL
−&agr;) when the output of the inverter is at a first logic level (e.g., logic 0) and at a second higher potential (e.g., V
DDL
) when the output of the inverter is at a second logic level (e.g., logic 1) opposite the first logic level.
According to one embodiment of the present invention, an integrated circuit buffer is provided that includes an inverter configured as a PMOS pull-up transistor having a gate electrode electrically coupled to an input node and a drain electrode electrically coupled to an output node, and an NMOS pull-down transistor having a gate electrode electrically coupled to the input node and a drain electrode electrically coupled to the output node. A diode and switch are also provided to perform the selective powering operation. The diode is provided to reduce the magnitude of the power supply signal the inverter receives when the PMOS pull-up transistor is inactive (thereby reducing the leakage current through the PMOS pull-up transistor) and the switch is provided to bypass the diode when PMOS pull-up transistor is active. According to a preferred aspect of this embodiment, the diode has a cathode electrically connected to a source electrode of the PMOS pull-up transistor and an anode electrically connected to a power supply signal line (e.g., V
DDL
). During a pull-up operation, the switch can be closed to bypass the diode by electrically connecting the source electrode of the PMOS pull-up transistor directly to the power supply signal line when the output node reaches a first logic potential (e.g., logic 1). Alternatively, the switch is opened when the output node is pulled down to a second logic potential (e.g., logic 0).
In order to provide a symmetric transfer characteristic, a resistor or diode is also preferably connected in series between a source of the NMOS pull-down transistor and a reference signal line (e.g., Vss). A NMOS pass transistor is also preferably provided in series between an input terminal of the buffer and the input node of the inverter. This NMOS pass transistor performs a level-shifting operation so that the buffer, which may be powered at CMOS power supply levels, may reliably receive signals at higher TTL levels, for example.
REFERENCES:
patent: 4475050 (1984-10-01), Noufer
patent: 4532439 (1985-07-01), Koike
patent: 4800303 (1989-01-01), Graham et al.
patent: 5087841 (1992-02-01), Rogers
patent: 5216299 (1993-06-01), Wanlass
patent: 5268599 (1993-12-01), Matsui
patent: 5300835 (1994-04-01), Assar et al.
patent:
Dinh Paul
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Wells Kenneth B.
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