Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-20
2002-12-10
Wong, Don (Department: 2821)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06493864
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor design apparatus and processes and, more particularly, to novel apparatus and methods for hierarchal handling of timing exceptions in a block model representation of an integrated circuit.
2. Description of the Background Art
During the performance of simulation and analysis of an integrated circuit, a block model representation of the integrated circuit is used. Each block model is an abstraction of a section of the integrated circuit. The abstraction is typically viewed on a display monitor of a workstation user interface, wherein the workstation reads data from an appropriate computer readable medium associated with the workstation. The medium may be internal to the workstation or readable over a local area, wide area, or public computer network.
The data, which is read, is commonly referred to as a netlist, the netlist being a textual representation of the contents of one block model. The netlist contains objects, which textually set forth the instances, modules, cell, terminals, ports, and nets and net segments, as well as the interrelation among them, thereby textually defining the block model.
Typically, the netlist is hierarchal. In a hierarchal netlist, the textual representation of the block model maintains only one copy of a module that may be used in multiple locations within the block model. When displayed in the user interface, the block model generated from the hierarchical netlist would show basic and non-repetitive devices in schematic form, and also would show each instance of the more complex and repetitive circuit modules as black box modules with only their input and output ports. The black box modules, although masking the complexities of the circuits therein, provide a known function between its input and output ports.
In the black box module, the allowed timing paths are either combinatorial or sequential. A combinatorial path proceeds from an input pin of the black box to an output pin, passing only through combinatorial logic. The combinatorial paths are modeled as pin to pin delays. A sequential path represents a convergence of data and clock inputs presented at multiple input pins, passing through clocked devices such as latches and gates, to an output pin. The sequential paths are modeled using setup and hold times, and may also include slope and load dependent delays with respect to the driving of an input or output pin.
Typically, a timing model is generated for each block model, and then subsequently the timing model for each block is combined with the timing model for each other block to determine the timing for the full chip. In generating the timing model for each block, it may be necessary to define certain timing path exceptions and exception operands for the block model.
For example, in a block model which may have two input pins, In
1
and In
2
, and two output pins, Out
1
and Out
2
, it may be necessary to define for one exception the path between In
2
and Out
1
as being disabled. The details of the path between these two pins cannot be seen at the top level block model since the path may contain instances of black box modules and lower level nodes within such modules. It may nonetheless be necessary to carry this exception along one or more paths between these instances and nodes to generate the timing model. It thus becomes desirable to see into the block model and raise such instances and nodes to the top level to define the timing exceptions necessary and generate the timing model.
It is possible to use a flat netlist for the block model, wherein the flat netlist contains data for all devices within the block model, including redundant data for repetitively used modules, thereby eliminating any hierarchy. The block model when viewed would accordingly contain all elements of the circuit, thus making it possible to see all nodes in the block model at a single level. However, not all nodes may need to be visible to define the timing exceptions, but only selected ones of the nodes may be required. Accordingly, it would become necessary to store significant amounts of extraneous data when using the flat netlist. Furthermore, in the block model which abstracts a portion of a complex integrated circuit, the additional amounts of data required to be stored for the flat netlist may be disadvantageously and prohibitively large.
Accordingly, there is a need for apparatus and methods for hierarchal handling of timing exceptions. There is a need for apparatus and methods for selecting only such nodes within modules as required for viewing at the top level. There is also a need for apparatus and methods which minimizes the amount of data stored in a data file.
SUMMARY OF THE INVENTION
According to the present invention, in a netlist that includes a plurality of objects, wherein the objects include a plurality of instances and a plurality of nodes, a method for handling of timing exceptions within the circuit or block model comprises marking selected ones of the nodes, generating a timing model having a plurality of timing arcs wherein each of the timing arcs are between any two of the selected ones of the nodes, creating exception signatures for the timing exceptions to be carried in the timing model in association with the timing arcs, and removing extraneous ones of the exception signatures from association with the timing arcs.
In one aspect of the present invention, the method set forth above may be implemented by a program embedded in a computer readable medium. The program when executed reads data, which may be contained in memory or in a readable file, containing information relating to the circuit or block model, similar to the description of the circuit or block model set forth above, and implements the above described method for hierarchal handling of user or software program inputted timing exceptions.
In another aspect of the present invention, a computer system for hierarchal handling of timing exceptions comprises a computer workstation including a user interface having at least a display monitor and an input device, and a storage medium usable by the workstation, wherein the medium includes data readable by the workstation and program code readable and executable by the workstation. The data contains information of a circuit or a block model similarly as set forth above. The program code causes the circuit or block model to be displayed on the monitor and further causes the input device to be responsive to a user inputted timing exceptions within the circuit or block model when displayed. The program code in response to the timing exceptions being inputted then causes the workstation to mark selected ones of the nodes. Next, the program code in response to the selected ones of the nodes being marked causes the workstation to generate a timing model having a plurality of timing paths wherein each of the timing paths are between any two of the selected ones of the nodes. Thereafter, the program code, in response to the timing model being generated, causes the workstation to create exception signatures for the timing exceptions to be carried along the timing paths. Finally, the program code in response to the exception signatures being created causes the workstation to remove extraneous ones of the exception signatures from the timing paths.
A feature of the present invention is that the selected ones of the nodes, which are marked, are made visible at the top level of the hierarchy irrespective of the level at which the marked nodes may be within the netlist. Exception signatures may now be carried along paths between these nodes. Another feature of the present invention is that extraneous exceptions signatures, being those signatures along paths wherein they could not exist, are removed from the data. Another feature of the present invention advantageously limits the amount of data that would be necessary when using a flat netlist wherein all nodes and modules are visible.
REFERENCES:
patent: 5463562 (1995-10-01), Theo
Ammocore Technology, Inc.
Cascio Anthony T.
Lee Wilson
Wong Don
LandOfFree
Integrated circuit block model representation hierarchical... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit block model representation hierarchical..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit block model representation hierarchical... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2992002