Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2011-06-28
2011-06-28
Hoang, Quoc D (Department: 2892)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C257SE21609
Reexamination Certificate
active
07968416
ABSTRACT:
An integrated circuit arrangement and fabrication method is provided. The integrated circuit arrangement contains an NPN transistor and a PNP transistor. The PNP transistor contains an emitter connection region and a cutout. The cutout delimits the width of the emitter connection region. The electrically conductive material of the connection region laterally overlaps the cutout.
REFERENCES:
patent: 6005284 (1999-12-01), Ejiri et al.
Böttner Thomas
Drexl Stefan
Huttner Thomas
Seck Martin
Brinks Hofer Gilson & Lione
Hoang Quoc D
Infineon - Technologies AG
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