Integrated circuit arrangement with capacitor

Details Integrated circuit arrangement with capacitor Integrated circuit arrangement with capacitor

2007-11-06

2007-11-06

Le, Thao P. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S347000, C257S351000

Reexamination Certificate

active

10529990

ABSTRACT:
An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.

REFERENCES:
patent: 6160269 (2000-12-01), Takemura et al.
patent: 6207985 (2001-03-01), Walker
patent: 6413802 (2002-07-01), Hu et al.
patent: 2001/0014047 (2001-08-01), Hidaka et al.
patent: 2002/0125536 (2002-09-01), Iwasa et al.
patent: 57176757 (1982-10-01), None
patent: 61113271 (1986-05-01), None
patent: 62259466 (1987-11-01), None
patent: 03173175 (1991-07-01), None
International Examination Report from corresponding PCT patent application No. PCT/DE03/03355, date unknown.
International Search Report from corresponding PCT patent application No. PCT/DE03/03355, Date: Sep. 8, 2004.

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