Integrated circuit arrangement having at least one MOS transisto

Details Integrated circuit arrangement having at least one MOS transisto Integrated circuit arrangement having at least one MOS transisto

1998-04-23

2000-05-23

Saadat, Mahshid

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257330, 257302, 257242, 257244, 257742, H01L 2976, H01L 2994, H01L 31062

Patent

active

060668768

ABSTRACT:
An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

REFERENCES:
patent: 5258635 (1993-11-01), Nitayama et al.
patent: 5302843 (1994-04-01), Yamazaki
Vertical MOS Transistors With 70nm Channel Length--Risch et al., Proceedings ESSDERC 1995.
Experimental Study Of Carrier Velocity Overshoot in Sub-0.1 .mu.m Devices-Physical Limitation of MOS Structures--Mizuno et al--1996 IEEE IEDM 96-109-112.
Vertical FET Gives NTT Twice The Chip Density--Electronics/Nov. 18, 1985.
IBM Technical Disclosure Bulletin--vol. 32 No. 8A, Jan. 1990--144.

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